DIL/NetPC Module Goes Open Source
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Two years after the Linux based embedded softcore computing module ADNP/ESC1 has launched, SSV publishes the circuit schematic, parts list, layout plan and all soft-ware source codes of the FPGA module.
With the GPL in mind the published sources can be used for developing and producing the ADNP/ESC1 by oneself. The main advantages of the FPGA module like the independence of obsolete processors and the - for an embedded computing platform - unequalled product lifecycle time are now freely available for everybody. Mechanically the DIL/NetPC ADNP/ESC1 is based on the 128-QIL socket and therefore compatible to other members of the DIL/NetPC module family.
The ADNP/ESC1 uses a 50-Mhz FPGA softcore processor instead of a common 32-bit stan-dard MCU. In addition to that the module includes a 10/100 Mbps Ethernet interface,
8 MByte Flash and 16 MByte SDRAM. As further interfaces there are two serial and one par-allel port, a compact-flash interface and a 16-bit expansion bus provided. As operating sys-tem a µCLinux with TCP/IP and several servers is used, which will be booted by the U-Boot boot loader.
For further information about the ADNP/ESC1 please contact SSV directly or visit www.dilnetpc.com
Reader enquiries:
SSV Embedded Systems
Heisterbergallee 72
30453 Hannover, Germany
Phone.: +49(511)4 00 00-0
Fax: +49(511)4 00 00-40
sales@ist1.de
ssv-embedded.com
