Digital I/O Modules implement user-configurable FPGA.
Press Release Summary:
Industry Pack IP-EP200 Series I/O Modules interface digital I/O signals to user-configurable Altera® Cyclone(TM) II FPGA. Several models are available to accommodate RS-485 differential, TTL, or LVDS digital I/O signals. All modules feature Cyclone II EP2C20 FPGA device with 20K logic elements, 240 Kb RAM, and 26 embedded multipliers. Series IP-EP200 allows users to develop and store their own instruction set in FPGA for adaptive computing applications.
Original Press Release:
New Industry Pack Digital I/O Module Is The First To Implement A User-Configurable Altera® Cyclone(TM) II FPGA
Acromag's new Industry Pack I/O modules provide a user-configurable FPGA for high-performance processing of custom logic routines and a digital I/O interface supporting a variety of signal types.
Wixom, MI: Acromag's new IP-EP200 series Industry Pack I/O modules interface digital I/O signals to a user-configurable Altera® Cyclone(TM) II FPGA. The IP-EP200 is the first Industry Pack (IP) module to implement the Cyclone II device, the highest-performing low-cost FPGA on the market, for use in processing user-defined algorithms and custom logic routines. And with JTAG access to the SignalTap® II embedded logic analyzer, engineers can easily monitor internal device operation. Several models are available to accommodate RS-485 differential, TTL, or LVDS digital I/O signals with prices starting at $1000. Extended temperature (-40 to 85°C) models are also available.
All units feature Altera's Cyclone II EP2C20 FPGA device with 20K logic elements 240Kb RAM, and 26 (18 x 18) embedded multipliers. One IP-EP200 model provides 48 bi-directional TTL I/O lines, another offers 24 differential RS485 I/O lines, and a third has 24 LVDS I/O lines. The "combo" model pairs 24 TTL with 12 RS485 I/O lines on a single IP module.
The IP-EP200 allows users to develop and store their own instruction set in the FPGA for adaptive computing applications. Typical uses include specialized communication systems over RS422/485 networks, test fixture simulation of signals over TTL-switched lines, and analysis of acquired data using specialized mathematical formulas such as those developed with MathWorks's MatLab® software. User application programs are downloaded through the JTAG port or via the IP bus directly into the FPGA.
A long list of features add flexibility and processing capability. To meet memory demands, 64K x 16 local static RAM is provided under FPGA control. An LVTTL external clock is also connected directly to the FPGA. The programmable PLL-based clock synthesizer generates frequencies from 250kHz to 100MHz. Support for both an 8MHz and a 32MHz IP bus is also standard.
