Digital Fanout Buffer offers adjustable inputs from -4 to +4 V.

Highland Technology Oct 16, 2009

Press Release Summary:

Suited to embedded OEM or benchtop use, P730 comes in anodized aluminum enclosure and features 2 input banks that are user-routable to 2 output banks comprised of 4 buffered electrical outputs. Input and output levels are independently adjustable, enabling compatibility with CMOS, TTL, LVDS, NECL, PECL, NIM, and sine wave systems. Fiber optic inputs are optionally available, and fully DC-coupled signal path maintains signal integrity to greater than 1 GHz pulse repetition rates.

Original Press Release:

Highland Technology Introduces the Model P730 High-Speed, Multipurpose Digital Fanout Buffer

Highland Technology introduces the Model P730 high-speed, multipurpose digital fanout buffer. Attractively housed in an anodized aluminum enclosure, the P730 is suited to embedded OEM or benchtop use. The P730 features two input banks that are user-routable to two output banks, each consisting of four buffered electrical outputs. Input and output levels are independently adjustable enabling compatibility with CMOS, TTL, LVDS, NECL, PECL, NIM and sine wave systems. Fiber optic inputs are optionally available, expanding electrical signal translation to include optical-to-electrical conversion, galvanic isolation and 1244.16 Mb/s SONET OC-24 compatibility. A fully DC-coupled signal path maintains signal integrity to greater than 1GHz pulse repetition rates. Features include:

Electrical logic input thresholds adjustable from -4V to +4V

Input-to-output bank assignment is routable without moving cabling

Programmable logic out bank voltages adjustable from -3.6V to +5V, 50 W source

850nm, 1310nm or 1550nm fiberoptic input options available with ST or FC connectors and calibrated 1V/mW analog front panel monitor output

Stable, ultra-low jitter, sub 350ps output edge transition times

Ideal for buffering fast electrical or optical logic signals, time codes, 1 PPS GPS or atomic clock pulses, and for facility clock distribution.

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