Design Software minimizes compilation times.
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Press Release Summary:
Quartus II Software v9.1 for CPLD, FPGA, and HardCopy® ASIC designs includes Rapid Recompile feature, which enables it to minimize design compilation times. Program supports Stratix® IV E EP4SE820 FPGA as well as VHDL 2008 flexible language structure that lets users create reusable code structures. Its SSN analyzer tool provides feedback on potential simultaneous switching noise violations during pin assignments. Software also supports Linux SUSE 10.
Original Press Release:
Altera Continues Its 2X to 3X Compile Time Advantage with Quartus II Software Version 9.1
Latest Software Release Adds Support for Altera's New Cyclone IV FPGA Family
San Jose, Calif., November 2, 2009 - Altera Corporation (NASDAQ: ALTR) today announced the release of Quartus® II software version 9.1, the industry's number-one software in performance and productivity for CPLD, FPGA and HardCopy® ASIC designs. New features and enhancements within Quartus II software v9.1 reduce compile times 20 percent versus the previous software release, while continuing to deliver on average 2X to 3X faster compile times compared to competing high-density 40-nm and 65-nm designs. New to the software is a Rapid Recompile feature, which significantly improves compile times for small design changes, as well as support for Altera's newly announced Cyclone® IV FPGAs.
Quartus II software v9.1 builds upon the productivity advantage Altera consistently delivers with its design software. The software provides the industry's fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually over the past five years. The compile time advantages in the latest release are driven by more efficient place and route algorithms, improved multiprocessor support and faster timing-driven synthesis.
Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances the Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes designer productivity when making small engineering change order (ECO)-style design changes after a full compile is run, reducing compilation times by 50 percent on average versus running another full compile on the design. Rapid Recompile also significantly improves designer productivity during timing closure by preserving critical timing during late design changes.
Expanded Device Support for New Cyclone IV FPGAs
The three smallest Cyclone IV GX devices will be supported in the Quartus II design software v9.1 with the remaining Cyclone IV devices supported in the Quartus II design software v9.1 service pack 1. To see the press release for the Cyclone IV family, announced today, visit www.altera.com/corporate/news_room/releases/2009/products/nr-cyclone-iv.html. This version of the Quartus II software also offers support for the Stratix® IV E EP4SE820 FPGA, the industry's highest density FPGA at 820K logic elements (LEs). Offering software support for Altera's latest FPGA families enables customers to get a jump start on the latest Cyclone and Stratix FPGA designs today.
Additional Features Within Quartus II Software Version 9.1 Include:
o Non-Rectangular Partitions with Incremental Compile-Non-rectangular regions help users create more compact and efficient floorplans, making it easier to achieve quality metrics. This new feature provides users a simpler and easier interface for finer control during design partitioning.
o Expanded SSN Analyzer Tool-With new support for Arria® II GX FPGAs and Stratix IV GX FPGAs, this tool provides feedback on potential simultaneous switching noise (SSN) violations during pin assignments.
o New and Expanded IP Base Suite-Three new memory controllers supporting RLDRAM II, QDRII / II+ and DDR1/2/3 increase the suite to 14 intellectual property (IP) cores.
o Initial Support for VHDL 2008-Quartus II software maintains its leadership in language support by providing a more flexible language structure that allows users to create reusable code structures.
o Nios® II Processor-The "/e" variant of the Nios II soft processor is now available without a license fee. This release also marks the debut of the Nios II software build tools for Eclipse, which provides improved software-development productivity.
o Expanded OS Support-Support for Linux SUSE 10 is now available.
For additional information about the features offered in Quartus II software v9.1, visit www.altera.com/q2whatsnew.
"Design teams today continue to look for ways to maximize productivity as they face the challenges of tighter budgets, shrinking R&D resources and truncated design schedules," said Chris Balough, senior director of software, embedded, and DSP marketing at Altera. "Quartus II software's increased productivity advantage ensures our customers can get their FPGAs to market quicker and with reduced engineering expenses."
Pricing and Availability
Both the Subscription Edition and the free Web Edition of the Quartus II software version 9.1 are currently available for download. Quartus II software subscribers receive the ModelSim Altera Starter Edition and a full license to the IP Base Suite, which includes 14 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera's eStore or from authorized distributors.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
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