CMOS Serial Link increases backplane port density.

Press Release Summary:

Model TLK6B008 enables 6 Gbps transmission over legacy system that run up to 3 Gbps. It has eight 6.25 Gbps bi-directional serial data channels on sharp end and sixteen 3.125 Gbps channels on blunt end, providing 100 Gbps data throughput. Receiver uses 4-tap adaptive DFE receive equalizer technology, including cancellation of first post cursor. Transmitter uses 4-tap equalizer with fully programmable coefficients at 5-bit resolution. Equalization compensates for ISI and cross talk.

Original Press Release:

TI Unveils 6.25Gbps CMOS Serial Link Technology

Enables Customers to Increase Port Density of Legacy Backplane Systems

DALLAS (Feb. 3, 2004) - Enabling 6 gigabit per second (Gbps) transmission over legacy system backplanes that currently run up to 3Gbps, Texas Instruments Incorporated (TI) (NYSE: TXN) today announced its first 6.25Gbps serial link product in its advanced CMOS technology. Further extending the company's expertise in high-speed serial and parallel I/O, this technology gives customers the ability to increase the port density of existing systems without having to replace legacy backplanes. (See

"The TLK6B008 capitalizes on TI's high-performance, cost-efficient CMOS process to meet communications equipment manufacturers' need to pack more ports in less space, while providing excellent signal integrity across marginal backplane environments," said Martin Izzard, director of the fiber optics and backplane business unit of TI's high-performance analog business. "This new technology enables our customers to offer more cost-effective, high performance equipment to network service providers and enterprise customers."

The TLK6B008 has eight 6.25Gbps bi-directional serial data channels on the sharp end and sixteen 3.125Gbps serial data channels on the blunt end, providing 100Gbps data throughput. The receiver uses 4-tap adaptive DFE (Decision Feedback Equalization) receive equalizer technology, including cancellation of the first post cursor. The transmitter uses a 4-tap equalizer with fully programmable coefficients at 5-bit resolution. This sophisticated equalization compensates for ISI and cross talk, which is essential for operating in legacy system environments.

The TLK6B008 extends the life span of today's XAUI (10G Ethernet) backplanes, thus preserving technology investments made by the system manufacturers. When coupled with TI's advanced design methodology, a 6.25Gbps macro also enables high density integration of many 6.25Gbps serial links on digital VLSI ASICs, including switch fabrics, to reduce overall system power, size and cost. The technology is available today in TI's ASIC library, providing an integration path for customers seeking higher performance in their network infrastructure products.

Key Features of the TLK6B008

o Octal 6.25G/3.12G/1.25Gbps MUX/1 DEMUX Device

o 4-Tap Adaptive Decision-Feedback (DFE) Receiver

o Programmable, 4-Tap, 5-bit Feed-Forward Equalized Transmitter

o Binary (PAM-2) NRZ Signaling

o 1.2/2.5 V Power Supply

o Low Jitter CML Serial Interface with On Chip Termination

o On-chip PLL for Clock Synthesis from Low Frequency Reference Clock

o Available in ASIC Core Library

Packaging and Availability

The TLK6B008 comes in a 19x19 pins full-array FC-BGA package with 1 mm ball pitch. The TLK6B008 is available for sampling now to partner customers. For more information on TI's serial gigabit products, please see the product bulletin at

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