Press Release Summary:
Six high-speed, programmable, clock dividers of SY89871 family meet ultra-low jitter and skew requirements in SONET/SDH communications systems, high-end enterprise server and router applications, and high-speed ATE and T&M systems. Precision 2.5 and 3.3 V clock dividers have patent-pending input stage with internal termination and accept any differential input source. Within-device skew is <15 ps, with jitter performance of <10 ps(pk-pk).
Original Press Release:
Lowest Jitter, Lowest Skew LVPECL & LVDS Programmable Clock Dividers with Internal Termination
o >2GHz Maximum Throughput
o Lowest Jitter Performance: <10ps(pk-pk)
o Lowest Skew Performance: <15ps
SAN JOSE, Calif. June 9th -- Six new high-speed, LVPECL and LVDS programmable clock dividers have been released from Micrel's Precision Edge(TM) Timing & Distribution family to meet the ultra-low jitter and skew requirements in SONET/SDH communications systems, high-end enterprise server and router applications, and high-speed ATE and T&M systems.
Micrel ( NASDAQ: MCRL
The SY89871/2/3/4/5/6 are precision 2.5V & 3.3V high speed LVPECL and LVDS programmable clock dividers with a unique, patent-pending input stage that includes internal termination and the ability to accept any differential input source. Whether the input signal is AC-coupled or DC-coupled, no external components are required in the signal path to interface to the SY89871 family. Furthermore, resulting stubs associated with external termination networks are eliminated, thus preserving the signal integrity.
The SY89871 family of non-PLL clock dividers is optimized for applications whichapplications which require the lowest jitter and skew performance. Within-device skew is guaranteed to be less than 15ps; rise and fall times are less than 250ps. Designed to accept a high frequency (e.g. 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal, this family divides down the frequency with programmable divider ratios of 1, 2, 4, 8 or 16 to create a frequency locked phase-aligned, clock subset of the input clock. For applications that require phase relationship between the reference input clock and the divided output frequency, the SY89871/2/3 features two output banks: one output that is the exact copy of the input, and a second, divided output with an integrated 1:2 fanout buffer. Both output banks feature a matched delay, independent of divider setting. The SY89874/5/6 have just one output bank for either straight pass-through or the divided outputs. A 1:2 fanout buffer with <15ps skew is also included in the output banks.
Designed for communications applications, the SY8987x family features a total jitter (defined as the amount of accumulated peak-to-peak jitter measured over 1012 clock cycles) of less than 10ps(pk-pk) over temperature and voltage. In addition, the SY89871 family is offered in a 16-pin (3mm x 3mm) MLF(TM) package, which represents a 70% reduction in footprint area compared to alternative solutions.
The SY89871U, SY89872U, SY89873L, SY89874U, SY89875U and SY89876L clock divider solutions have been released to production, and pricing starts at $4.40 (1,000-piece suggested resale, FOB USA). The SY89871 family is offered in a small (3mm x 3mm) 16-pin MLF(TM) package and guaranteed over the -40°C to +85°C industrial temperature range.
Micrel Semiconductor is a leading manufacturer of advanced, precision edge timing and distribution, Ethernet switch and physical layer transceiver, mixed signal, analog and power IC solutions. These products include devices for fiber-optic telecommunications and networking, cellular telephones, servers, portable computer systems, computer peripherals, process control systems, consumer electronics and power supplies.