Press Release Summary:
Available in 65 nm and 40 nm process technologies for ASIC integration, burst-mode CDR SerDes PHY chip can lock to upstream data burst at 2.488 Gbps in less than 16 bits. Device is also available as standalone chip for supporting reference designs. In addition, CDR SerDes can be configured to optimize burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gbps. With high-jitter tolerance of 0.6 UI in burst mode operation, chip suits variety of optical transceivers.
Original Press Release:
K-micro Announces Availability of Burst-mode CDR for XGPON1 OLT Applications
CDR SerDes PHY for XGPON1 OLT available for ASIC integration and as a standalone chip
SAN JOSE, Calif., -- K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced PON ASICs, announced a new burst-mode CDR SerDes PHY for XGPON1 OLT applications. Available now in 65nm and 40nm process technologies for ASIC integration, this chip can lock to upstream data burst at 2.488 Gb/s in less than 16 bits. The new SerDes is also available as a standalone chip for supporting reference designs. In addition, the CDR SerDes can be configured to improve burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gb/s.
"Having a multi-function high performance SerDes will enable our customers to provide a wide range of solutions with a single chip," said Dr. Vijay Pathak, US CTO of K-micro. "With the availability of the new CDR SerDes for XGPON, K-Micro ASIC solutions can cover all the PON standards - BPON, EPON, GPON, 10G EPON, and XGPON1. The company leads PON PHY technology with its world-fastest lock time, 50ns, CDR for 10G EPON OLT, and provides highly integrated ASIC solutions for PON applications. In the future, K-micro will extend this capability to even higher data rates and provide OLT SerDes solutions for next-generation XGPON1 networks."
The SerDes has total flexibility and can be tailored according to optical transceiver characteristics and other system characteristics and latencies. The CDR has a high-jitter tolerance of 0.6 UI in burst mode operation enabling it to be used with a large variety of optical transceivers. Outside the burst-mode operation, the CDR works in continuous mode where it can tolerate even higher jitter.
Other key features include:
1. Smart BIST - Ability to test in production a variety of test patterns which emulate a real system environment
2. High-Jitter tolerance
3. Low-Jitter generation
4. Easily configured for all ONU and OLT applications in 10G XGPON1, GPON and EPON
The evaluation chips are available now and are available to qualified ASIC customers at no charge.
About K-micro (Kawasaki Microelectronics America)
K-micro's innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking, and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), International Telecommunication Union (ITU) and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit www.k-micro.us