Press Release Summary:
Providing 4 ADCs in 7 x 8 mm QFN package, quad-channel Series LTC2175 features 14-bit resolution from 25-125 MSps, SNR of 73.4 dB, and SFDR of 88 dB at baseband. Data is output in serial LVDS format to minimize number of data lines. SPI-compatible interface allows users to choose between variety of data settings that minimize digital feedback. Operating from 1.8 V analog and digital supplies, devices include sleep mode that reduces power dissipation to 1 mW.
Original Press Release:
LTC2175 : Quad/Dual 14-Bit, 125Msps ADCs Dissipate One-Third the Power
MILPITAS, CA - July 28, 2009 - Linear Technology Corporation announces a family of 24 ultralow power 14-bit/12-bit, 125Msps to 25Msps, quad and dual ADCs that dissipate as little as one-third the power of competing ADCs. The flagship ADC is the LTC2175-14, a quad 14-bit, 125Msps ADC that dissipates only 558mW (140mW per channel). The LTC2175 significantly reduces system power without sacrificing AC performance, offering signal to noise ratio (SNR) performance of 73.4dB and spurious free dynamic range (SFDR) of 88dB at baseband. Operating from 1.8V analog and digital supplies, the LTC2175 includes a sleep mode that reduces power dissipation to just 1mW. Whether operating at full speed or in sleep mode, this ADC significantly lowers the power budget for highspeed multichannel designs such as multiple-input multiple-output (MIMO) WiMAX/LTE and 3G basestations, portable medical imaging and non-destructive testers.
Data is output from the LTC2175 in serial LVDS format to minimize the number of data lines. At 125Msps, each channel outputs two bits at a time, using two lanes per ADC. At lower sample rates, a one bit per channel option is available. The LTC2175 offers serial data communication and four ADCs in a small 7mm x 8mm QFN package, requiring less board area for data I/O lines and simplified layout.
The LTC2175 includes an SPI-compatible interface that allows users to choose between a variety of data settings that reduce digital feedback and simplify design. Options include a data output randomizer that reduces digital feedback, seven programmable LVDS output current levels, internal 100Ohm LVDS output termination resistors, and digital output test patterns. These settings can be programmed via SPI or hard-wired for a reduced set of operating modes.
The LTC2175 is part of a family of pin-compatible quad ADCs, offering 14-bit and 12-bit resolution from 25Msps up to 125Msps. All devices are supported with demonstration boards and free software for quick device evaluation, available online at www.linear.com and www.linear.com/designtools/software. 14-bit and 12-bit dual versions of this family in 6mm x 6mm QFN packages will be available in production quantities by October. For more information, visit www.linear.com.
SUMMARY OF FEATURES: LTC2175/LTC2268 FAMILIES
o Quad/Dual-Channel Simultaneous Sampling ADCs (LTC2175/LTC2268)
o 73.4dB SNR (14-Bit Resolution)
o 88dB SFDR
o Low Power: 558mW (140mW/channel) at 125Msps (LTC2175)
o Single 1.8V Analog & Digital Supplies
o Serial LVDS Outputs
o Selectable Input Ranges: 1VP-P to 2VP-P
o 800MHz Full-Power Bandwidth S/H
o Optional Data Output Randomizer
o Optional Clock Duty Cycle Stabilizer
o 1mW Sleep and 50mW Nap Modes
o Serial SPI Port for Configuration
o Pin Compatible 14-Bit and 12-Bit Versions
o 52-Pin (7mm x 8mm) QFN Package (Quad Versions)
o 40-Pin (6mm x 6mm) QFN Package (Dual Versions)