License-free, FPGA-Based Single Chip Controller for Low Cost SERCOS III I/Os Available
SERCOS International has introduced Easy-I/O, a free IP core software for low-cost FPGA chips, which allows SERCOS III to be integrated into basic I/O slave devices with minimal development and integration effort. This is another important milestone in the establishment of SERCOS III as a universal, low-cost real-time Ethernet solution for motion and I/O.
Typical target applications of Easy-I/O are encoders, measuring sensors, valve clusters, 24V digital I/O and analog I/O.
Easy-I/O can be very easily integrated in hardware designs. A free version of the core is provided for the Xilinx Spartan-3 XC3S250E device in a TQ144 housing. It supports 16 digital inputs and 16 digital outputs.
To provide easy access for interested companies, SERCOS International will offer Easy-I/O as a freely downloadable IP core via sercos.de/easy-io, to be active by the end of May. Companies simply need to register online. There are no license fees and a membership in the SERCOS Organizations is not required.
Registered users receive the IP core, as well as a functional description, complete documentation of the interfaces and a reference design. Technical support is provided via an online forum and FAQ lists. Updates and bug fixes of the IP core will be provided on a regular basis.
Background information:
To minimize the costs for a slave interface, the functionality of a SERCOS III slave was reduced to a minimum. Thus, the Easy-I/O IP core supports only the SERCOS III real-time and service channels. Up to 64-byte master real-time data and 64-byte slave real-time data can be processed. Ethernet frames that are transmitted within the Non-Real-Time (NRT) channel of a SERCOS III network are directly forwarded to the next network node. The asynchronous service channel is realized inside the IP Core and allows read and write access to the available parameter according to the standardized SERCOS III I/O profile. Easy-I/O supports the remote addressing functionality of SERCOS III, by which a SERCOS address is assigned to a node on the basis of a physical address and a specific device identification. The core supports cycle times down to 31.25 µs as well as the unique redundancy feature of SERCOS III to provide highly available automation concepts.
