Cadence to Showcase System Design and Verification Solutions at DVCon 2016
Demos to highlight System Development Suite technologies including Palladium Z1, JasperGold, Stratus, Indago, Perspec, Protium and Verification IP
SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it plans to showcase the Cadence® System Development Suite and its most recent innovations during this year's DVCon in booth #505. The conference will be from February 29 to March 3, 2016, in Santa Clara, Calif.
To register for the conference, visit https://dvcon.org/rates.
WHAT:
The booth demonstrations will highlight the following Cadence system design and verification technologies:
   -- Hardware/software development featuring Palladium® Z1 and Protium™
       platforms
   -- SoC and subsystem verification featuring Incisive® platform and
       JasperGold® Apps
   -- IP creation and verification featuring Stratus™ High-Level Synthesis
       and Verification IP
   -- Debug, safety and analysis featuring Indago™ Debug Platform,
       Incisive® Functional Safety Simulator, and analog/mixed-signal and
       low-power technologies
Cadence is also scheduled to deliver several speaking sessions to discuss new technology developments and how they can help solve today's system design and verification challenges. The scheduled Cadence speaking sessions are:
   -- Tutorial: Cut Your Design Time in Half with Higher Abstraction, 2 p.m.
       to 5 p.m. on Monday, February 29
   -- Regular Session: Modeling Analog Systems Using Full Digital Simulations,
       a State Space Approach, 9 a.m. to 10:30 a.m. on Tuesday, March 1
   -- Poster Session: A Holistic Approach to Low-Power Mixed-Signal Design
       Verification Using Power Intent, 10:30 a.m. to noon on Tuesday, March 1
   -- Poster Session: DVS Interface Elements - A Novel Approach in Multi-Power
       Domain, Mixed-Signal Design Verification, 10:30 a.m. to noon on Tuesday,
       March 1
   -- Poster Session: A Complete SystemC Process Instrumentation API and its
       Application to Simulation Performance Analysis, 10:30 a.m. to noon on
       Tuesday, March 1
   -- Panel: Redefining ESL, 8:30 a.m. to 9:30 a.m. on Wednesday, March 2
   -- Lunch Panel: Software-Driven Verification with Portable Stimulus: The
       Next Productivity Leap Enabling the Continuum of Verification Engines,
       noon to 1:15 p.m. on Wednesday, March 2
   -- Tutorial: Methodology for Addressing Mixed-Signal SoC Verification
       Challenges, 8:30 a.m. to noon on Thursday, March 3
   -- Tutorial: Using Portable Stimulus for SoC Verification as Applied on
       Mobile, Networking, and Server Designs, 8:30 a.m. to noon on Thursday,
       March 3
   -- Tutorial: It All Starts with Quality Design, 2 p.m. to 5:30 p.m. on
       Thursday, March 3
WHEN:
February 29 to March 3, 2016
WHERE:
Booth #505 at DVCon 2016
Doubletree Hotel
2050 Gateway Pl, San Jose, CAÂ 95110
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Incisive, JasperGold and Palladium are registered trademarks, and Indago, Perspec, Protium and Stratus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.comÂ
SourceÂ
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com
