Cadence and Applied Materials Collaborate on Joint Development Program to Optimize Planarization Process through Advanced CMP Modeling

SAN JOSE, Calif. and SANTA CLARA, Calif. — Cadence Design Systems, Inc. (NASDAQ: CDNS) and Applied Materials, Inc. (NASDAQ: AMAT) today announced the companies are collaborating on a development program to optimize the chemical-mechanical planarization (CMP) process through silicon characterization and modeling for advanced-node designs at 14 nanometer (nm) and below. The program allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which is increasingly critical for advanced FinFET architectures.

The Cadence® and Applied Materials joint development program is focused on front end-of-line (FEOL) and wafer-level CMP modeling. Applied Materials can use the Cadence CMP Process Optimizer, a tool that allows silicon calibration of semi-physical models and optimization of CMP material and process parameters such as pressure, polish time and overall CMP uniformity, to enhance the precision performance of its Reflexion® LK Prime™ CMP system.

Once models are calibrated, design teams can leverage Cadence CMP Predictor, a tool that enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction. It provides full-chip, multi-level CMP thickness and topography predictions for shallow trench isolation (STI) and replacement metal gate (RMG) CMP processes. For more information on Cadence CMP Predictor and Cadence CMP Process Optimizer, please visit

Applied Materials is an industry leader in precision CMP technology with its Reflexion LK Prime CMP system that offers high-speed planarization and multi-zone polishing heads to enable superior uniformity and efficiency with low downforce for extendibility to <14nm device generations. The Reflexion LK Prime CMP system also implements a full suite of advanced process control capabilities that ensure excellent within-wafer and wafer-to-wafer process uniformity control and repeatability for all planarization applications.

"Working together with Cadence, we're driving advances in CMP process performance," said Derek Witty, vice president and general manager of the CMP Products Group at Applied Materials. "From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster."

"Cadence CMP Predictor helps turn the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "The joint development program with Applied Materials can allow us to drive advancements in CMP modeling processes so our design and manufacturing customers can maximize design yield and performance."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at

About Applied Materials

Applied Materials, Inc. (NASDAQ: AMAT) is the global leader in materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries. Our technologies help make innovations like smartphones, flat screen TVs and solar panels more affordable and accessible to consumers and businesses around the world. Learn more at

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