Cadence Design Systems, Inc.

Printing & Duplicating Equipment

PCB EDA Software makes design cycles shorter and predictable.

Promoting efficiency and productivity for PCB designers, Allegro® 16.6 includes Allegro PCB Designer Manufacturing Option that helpsÂ- streamline development of release-to-manufacturing package for products. Allegro Rules Developer and Checker, also included, offers single source for all design rules checks (DRCs) within PCB, lets users develop custom fabrication and...

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Electrical Equipment & Systems

Cadence to Showcase Latest RF Solutions at International Microwave Symposium 2015

SAN JOSE, Calif. –Â- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it plans to showcase its Virtuoso® Custom IC platform, Spectre® RF Simulation solution and Allegro® PCB RF solution at the International Microwave Symposium, an annual international meeting for technologists involved in all aspects of radio frequency integrated circuits (RFICs) and...

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Software

Media Alert: Cadence to Demonstrate 16FF+ and 10nm Design Solutions at TSMC Technology Symposium 2015

SAN JOSE, Calif.Â- — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is scheduled to demonstrate 16-nanometer (nm) FinFET Plus (16FF+) and 10nm advanced-node technologies that optimize customer designs and manufacturing efficiency at this year's TSMC 2015 Technology Symposium at booth 103 on April 7, 2015, in San Jose, Calif. WHAT: Cadence is planning to hold several...

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Software

Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry

Cadence Virtuoso Liberate Characterization Solution and Spectre Circuit Simulator Together Enable Accurate 14nm Logic Libraries SAN JOSE, Calif. –Â- Cadence Design Systems Inc. (NASDAQ: CDNS) and Intel Corporation today announced that the two companies have delivered a 14nm (nanometer) library characterization reference flow for customers of Intel Custom Foundry, continuing their...

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Software

SoC Implementation Software accelerates optimized design delivery.

Driven by massively parallel architecture, Innovus™ Implementation System helps SoC developers accelerate delivery of designs with optimized power, performance, and area (PPA). Physical implementation solution typically provides 10%–20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10 nm FinFET processes and established process nodes. Features include...

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Software

Brite Semiconductor Improves Quality of Results and Reduces Time to Market for Four SoC Designs with Cadence Digital Implementation and Signoff Tools

SAN JOSE, Calif. –Â- Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that Brite Semiconductor Corporation, used Cadence® digital implementation and signoff tools to complete four 28nm system-on-chip (SoC) designs and reduced their time to market by three weeks compared to previous design methodologies. By using Cadence tools, Brite Semiconductor was also able to increase...

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Software

Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process

Multi-protocol PHY supports PCI Express 2.0, PCI Express 3.0, USB 3.0 and SGMII specifications SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express® (PCIe®) 2.0 and PCIe 3.0 technology for TSMC's 16nm FinFET Plus (16FF+) process have passed PCI-SIG® compliance...

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Software

EDA Software offers system-level design/synthesis platform.

Offering consistent environment from TLM through gatesÂ- to maximize design and verification quality, Cadence® Stratus™ can be utilized across entire SoC design and addresses such real world challenges as ECO, low power, IP reuse, and routing congestion. Platform integrates Forte and Cadence technology and leverages sixth-generation, high-level...

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Printing & Duplicating Equipment

Media Alert: Cadence to Showcase Computational Lithography and Design for Manufacturing Solutions at SPIE 2015

SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it plans to exhibit its latest Design for Manufacturing (DFM) Physical Signoff and Computational Lithography technologies at this year's SPIE Advanced Lithography Exhibition at booth 227 from February 22 to 26, 2015, in San Jose, CA. To register for the conference, visit http://www.cadence.com/news/spie. WHAT:...

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Services

Cadence Offers Complete Development Environment for ARM Premium Mobile IP Suite

ARM and Cadence collaboration helps designers achieve faster time to market with ARM Cortex-A72 processor, ARM Mali-T880 GPU and ARM CoreLink CCI-500 System IP SAN JOSE, Calif.Â- – Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM today announced the availability of a complete system-on-chip (SoC) development environment supporting the new ARM premium mobile IP suite that incorporates...

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