Cadence Design Systems, Inc.
San Jose, CA 95134
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Cadence Modus Test Solution Enables Support for Safety-Critical SoC Designs Using ARM MBIST Interface
Highlights: - Collaboration helps customers reduce the need for manual work and speed time to market - Cadence and ARM complete silicon validation using ARM Cortex-A73 processor SAN JOSE, Calif., Nov. 14, 2016 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Modus™ Test Solution now supports the ARM® Memory Built-In Self Test (MBIST) interface, enabling...
Read More »Cadence RAK for ARM Cortex-M23 and Cortex-M33 processors.
Creating low-power ARM Cortex-M23 and Cortex-M33 processors, Cadence’s Rapid Adoption Kit address the development of secure IoT rapidly and efficiently. Consisting of end-to-end digital implementation and signoff flow, RAK enables quick silicon delivery of ARM-based applications. Features optimal power, performance and area, fast runtimes and efficient design closures and implementation of IoT...
Read More »Cadence Enables Customer Innovation with ARM-Optimized Solutions from Chips to Boards to Systems at ARM TechCon 2016
SAN JOSE, Calif., Oct. 18, 2016 -Â- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it will showcase ARM®-optimized solutions from chips to boards to systems at ARM TechCon 2016. The event is being held October 25-27, 2016, in Santa Clara, Calif., with Cadence®, a diamond sponsor, in booth 200. To register for the conference, visit www.armtechcon.com. WHAT: Cadence...
Read More »TSMC's System Design Solution for advanced wafer-level Integrated Fan-Out (InFO) packaging technology.
With analysis tools that enable concurrent multi-chip optimization for designs using InFO, this design solution includes multiple IC signoff solutions including, the Tempus™ Timing Signoff Solution, the Voltus™-Sigrity Package Analysis that offer multi-die concurrent electro-migration IR drop (EMIR) analysis, and the Cadence Physical Verification System (PVS), which provides DRC and layout...
Read More »Processor Architecture has optimized floating-point scalability.
To meetÂ- DSP application demands, 12th generation Tensilica® Xtensa® base processor architecture makes technologies available for customization and increases floating-point choices from 2 to 64 FLOPS/cycle. Features include click-box options for Tensilica Vision P6 DSP and Fusion G3 DSP and ConnX BBE DSP support. Additional tools include hardware floating-point ABI for...
Read More »ARM Cortex-R52 CPU Kit fosters accelerated adoption and use.
Cadence® RAK (Rapid Adoption Kit) is optimized for ARM® Cortex®-R52 CPU, which targets embedded designs forÂ- automotive, medical, and industrial safety applications. Solution, which consists of complete digital implementation and signoff flow, works with ARM Artisan® physical IP to help designers meet challenging PPA (power, performance, and...
Read More »Cadence to Showcase Latest PCB Design Tools at PCB West 2016
New Allegro and OrCAD Solutions Accelerate Development of Flex, Rigid-Flex Designs SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) will be featuring its latest scalable OrCAD® and Allegro® technologies at PCB West 2016 booth #400 from September 13-15 2016, in Santa Clara, Calif. To register for the conference, visit www.pcbwest.com. WHAT: Cadence will be holding...
Read More »Multi-Purpose DSP targets compute-intensive SoC designs.
With Xtensa instruction-set architecture, quad 32-bit integer MACs, and quad single-precision 32-bit floating-point MACs, Cadence® Tensilica® Fusion G3 Digital Signal Processor supports compute-intensive applications including radar, imaging, and mid- to high-end audio pre/post-processing. Unit offers comprehensive data-type support with auto-vectorization. DSP provides real-time...
Read More »Media Alert: Cadence to Showcase Multi-Purpose, Low-Power DSP at Linley Mobile & Wearables Conference 2016
SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that David Heine, senior design engineering architect, is scheduled to present a paper on multi-purpose, low-power DSPs for mobile and other markets at the Linley Mobile Wearables Conference on July 27, at the Hyatt Regency in Santa Clara, CA. The two-day conference runs July 26-27. WHAT: David Heine is scheduled to...
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