Synopsys, Inc.
Mountain View, CA 94043
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Tx/Rx Controllers and PHY IP support HDMI 1.4.
Targeting DTV and home theater applications, DesignWare-® HDMI(TM) IP solution supports features of HDMI 1.4 specification, including HEAC 3D formats, real-time content signaling, 4 K x 2 K resolution, and 10.2 Gbps aggregate bandwidth. HEAC block facilitates connectivity between internet-enabled digital home devices by enabling transfer of Ethernet and audio frames through single HDMI cable....
Read More »USB 3.0 Protocol Analyzer delivers graphical debug solution.
DesignWare-® USB 3.0 Protocol Analyzer simplifies debug of SuperSpeed USB 3.0 and 2.0 interfaces on SoCs by providing graphical view of protocol traffic. It helps users identify unexpected patterns in design traffic and then switches to detailed view of packet information to determine cause. High-level color-coded summary view and detailed symbol-view of individual packets and payloads...
Read More »System-Level Library features SuperSpeed USB 3.0 support.
Part of DesignWare System-Level Library, SuperSpeed USB 3.0 Transaction-Level Models support Open SystemC(TM) Initiative TLM-2.0 API specification, and are TLM representations of DesignWare-® SuperSpeed USB 3.0 Device and xHCI Host Controller IP. Models enable pre-RTL and pre-silicon software development, verification, and architecture exploration. They work in any IEEE1666-compliant SystemC...
Read More »Audio Codec IP helps designers increase SoC functionality.
Built on SMIC 65 nm process, DesignWare-® 96 dB Hi-Fi Audio IP helps designers integrate important audio functions into SoCs for consumer electronic applications. Record channel includes features such as ADCs, volume control, channel filters, microphone biasing, and microphone amplifiers, while playback channel includes elements such as DACs, channel filters, mixers, volume control, as well as...
Read More »EDA Software addresses signoff bottlenecks.
By utilizing distributed and threaded multi-core processing in tandem, PrimeTime(TM) 2009.12 enables design teams to achieve optimal runtime performance across heterogeneous multicore compute environments. Static timing and signal integrity analysis tool provides distributed multi-scenario analysis, which allows designers to perform timing analysis and ECO fixing simultaneously across multiple...
Read More »EDA Software suits pin-limited semiconductor testing.
Extending adaptive scan technology with low-pin interface to tester, DFTMAX(TM) compression allows designers to achieve predictable compression of up to 100x or more with one pair of test data pins. It generates high-speed tester interface that serializes test data, maximizing test data volume and limiting test application time. It is built into Galaxy(TM) Implementation Platform to eliminate...
Read More »PHY IP supports 28 nm processes in 1.8 V architecture.
Designed for smartphones, mobile Internet devices, and netbooks, DesignWare-® USB 2.0 picoPHY IP supports Battery Charging v1.1 specification, which allows mobile devices to draw up to 1.8 A of current when connected to wall charger. By supporting USB On-the-Go v2.0 specification, DesignWare USB 2.0 picoPHY incorporates Attached Detection Protocol feature, which optimizes power efficiency of...
Read More »Transmit/Receive Controller supports HDMI.
Available in process technologies from 90 nm down to 40 nm, DesignWare HDMI(TM) transmitter and receiver digital controllers and PHY IP solution supports high-bandwidth digital content protection. It offers comprehensive set of IP deliverables that help designers embed complex interface into next generation multimedia SoCs. Solution includes optimized analog front end to support longer HDMI...
Read More »Electronic Design Automation Software facilitates, accelerates ASIC/FPGA development.
Synphony HLS integrates M-language and model-based synthesis to promote design and verification productivity for communications and multimedia applications. Able to create optimized RTL for ASIC and FPGA implementation, architecture exploration, and rapid prototyping, solution also complements flows based on C/C++ by generating C-models for system validation and early software development in...
Read More »PHY and Controller IP supports 1,866 and 2,133 Mbps data rates.
Supporting Low Voltage DDR3L specification that runs at 1.35 V, DesignWare-® DDR3/2 PHY and Digital Controller IP targets digital home, digital office, data center, and storage applications that require bandwidth in excess of 1,066 Mbps per pin. IP includes PHY Utility Block with built-in data training circuits to enable in-system calibration. As part of data training sequence, DDR3/2 IP...
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