Mountain View, CA 94043
Dual-Core Processor supports HD audio applications.
Occupying 0.81 mm-² in 65 nm LP process, DesignWare(TM) ARC(TM) AS 221 BD is optimized for HD audio SoCs targeting Blu-ray Disc and Pulse Code Modulation 192 kHz/24-bit digital audio streaming applications. Processor delivers 3.5 Giga operations per second and consumes 0.26 mW/MHz. Unit includes complete software stack with all required codecs, media streaming framework, and Blu-ray Disc use...Read More »
Lighting Design Software speeds product validation process.
LightTools-® v7.1 illumination design and analysis software validates a system's color quality, light distribution, and other key performance metrics. It supports IES photometry types A and B, simplifying analysis of sources with non-rotationally symmetric output. Users can also superimpose illuminance data on any user-defined plane in 3D model, as well as calculate spatial or angular color...Read More »
Synopsys Expands Synthesis-Based Test Technology to Increase Designer Productivity
Unveils Plan to Accelerate Implementation of Higher Quality, Lower Cost Test MOUNTAIN VIEW, Calif. -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced plans to expand test technology embedded in Synopsys' RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis...Read More »
Configurable IP minimizes embedded memory transient errors.
Targeted at automotive, aerospace, and high-end computing applications, DesignWare-® STAR ECC Self-Test and Repair Error Correcting Codes IP helps SoC designers minimize transient failures found in semiconductor technologies. Unit provides optimal performance of partial word writes and error detection/correction capability in multi-bit upsets and random bit errors. Working with DFTMAX(TM)...Read More »
New Synopsys HSPICE Precision Parallel Technology Delivers up to 7X Speed-up for Analog/Mixed-Signal Designs
HSPICE 2010 Advanced Analysis Features Provide a High-performance Analog Verification Solution MOUNTAIN VIEW, Calif., -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today unveiled new HSPICE-® Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analog and...Read More »
FPGA Synthesis Software facilitates team design efforts.
Supporting iCE65 family of low-power FPGAs, 2010.09 release of Synplify Pro-® and Synplify-® Premier allow geographically distributed teams to work on portions of FPGA designs in parallel. Synplify Premier supports full suite of datapath and building block components within DesignWare Library. Both enable design blocks to be created and shared internally, and team members can take snapshot of...Read More »
Controller and PHY IP meets MIPI DigRF v3 and v4 standards.
Available in 40 nm process technologies, DesignWare MIPI M-PHY IP implements all required physical layer functionality defined in MIPI DigRF v4 specification. Integrated analog Phase Lock Loop and biasing block help guarantee integrity of high-speed clocks and signals required to meet strict timing requirements of protocol. In addition, DesignWare MIPI M-PHY supports optional dithering...Read More »
Hi-Fi Audio IP is offered in 40 and 55 nm process technologies.
Available in 40 and 55 nm process technologies, DesignWare-® 96 dB Audio IP targets consumer electronic applications requiring Hi-Fi playback and record capabilities with minimal power consumption and silicon area. Modular nature lets designers select specific features for target applications, while function set covers signal processing, signal conditioning, clock management, power management,...Read More »
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances
HyperScale Technology Delivers 5 to 10X Boost in Performance and Capacity MOUNTAIN VIEW, Calif., -- Synopsys, Inc. (NASDAQ:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today unveiled new PrimeTime-® HyperScale technology that enables static timing analysis (STA) to scale beyond 500 million instances. PrimeTime HyperScale technology provides...Read More »
EDA Software generates SoC design libraries.
Based on Synopsys' HSPICE-® circuit simulation, StarRC(TM) extraction, NanoTime transistor-level timing, and Liberty(TM) NCX library modeling technologies, Galaxy Characterization Solution delivers precise timing, noise, and power models for standard cells, macros, and memories in compact composite current source library format. Compact CCS models feed into IC Compiler physical implementation...Read More »