Synopsys, Inc.
Mountain View, CA 94043
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Illumination Design Software models freeform optics.
With Advanced Design Module, LightTools-® v8.3 enables modeling of reflective and refractive freeform optics in both single-surface and segmented configurations for diverse set of illumination applications. Software also assists designers in modeling spatial temperature and power density variations in phosphor-based LEDs. API lets users develop custom volume scattering components, while Volume...
Read More »Illumination Design Software models freeform optics.
With Advanced Design Module, LightToolsÃ-® v8.3 enables modeling of reflective and refractive freeform optics in both single-surface and segmented configurations for diverse set of illumination applications. Software also assists designers in modeling spatial temperature and power density variations in phosphor-based LEDs. API lets users develop custom volume scattering components, while...
Read More »Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
Delivers Higher Frequency and Smaller Area Compared to Other Synthesis Solutions MOUNTAIN VIEW, Calif.- — Highlights: • Key ASIC has deployed Design Compiler Graphical to accelerate the design implementation of its consumer, wireless and personal electronics ICs • Comprehensive evaluation of available synthesis tools demonstrated Design Compiler Graphical's benefits of improved timing QoR...
Read More »Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
Delivers Higher Frequency and Smaller Area Compared to Other Synthesis Solutions MOUNTAIN VIEW, Calif.Ã- — Highlights: • Key ASIC has deployed Design Compiler Graphical to accelerate the design implementation of its consumer, wireless and personal electronics ICs • Comprehensive evaluation of available synthesis tools demonstrated Design Compiler Graphical's benefits of improved timing...
Read More »Intel Custom Foundry Certifies Synopsys Implementation Tools for 14-nm FinFET Production
Galaxy Design Platform-based Implementation Flow Available Today for 14-nm MOUNTAIN VIEW, Calif. – Highlights: -   -- Silicon-proven digital and custom implementation tools from the Galaxy        Design Platform are now certified for foundry customers on Intel's 14-nm        process    -- Silicon-proven Synopsys DesignWare IP...
Read More »Intel Custom Foundry Certifies Synopsys Implementation Tools for 14-nm FinFET Production
Galaxy Design Platform-based Implementation Flow Available Today for 14-nm MOUNTAIN VIEW, Calif. – Highlights: Ã- ÃÂ ÃÂ --ÃÂ Silicon-proven digital and custom implementation tools from the Galaxy ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ ÃÂ Design Platform are now certified for foundry customers on Intel's 14-nm...
Read More »Power Controller/PHY IP Solution reduces mobile SoC energy draw.
Reducing active and standby power consumption for mobile SoCs, Synopsys DesignWare-® IP for PCIe® 3.1 specification helps designers extend mobile device battery life. L1 sub-states and power gating techniques, including utilization of power switches, power islands, or retention cells, reduce standby power to
Read More »Power Controller/PHY IP Solution reduces mobile SoC energy draw.
Reducing active and standby power consumption for mobile SoCs, Synopsys DesignWareÃ-® IP for PCIeî 3.1 specification helps designers extend mobile device battery life. L1 sub-states and power gating techniques, including utilization of power switches, power islands, or retention cells, reduce standby power to
Read More »Silicon-Proven IP offers 16 nm FinFET Plus processes.
DesignWare-® PHY IP for TSMC's 16 nm FinFET Plus processes (16FF+GL and 16FF+LL) enables designers to accelerate development of SoCs that incorporate embedded memories and interface IP for USB 3.0/2.0 and HSIC; PCIe® 4.0/3.0/2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3; and LPDDR4/3/2 protocols. Also available, DesignWare Logic Libraries for TSMC 16FF+ processes include 7.5-, 9-, and 10.5-track...
Read More »Silicon-Proven IP offers 16 nm FinFET Plus processes.
DesignWareÃ-® PHY IP for TSMC's 16 nm FinFET Plus processes (16FF+GL and 16FF+LL) enables designers to accelerate development of SoCs that incorporate embedded memories and interface IP for USB 3.0/2.0 and HSIC; PCIeî 4.0/3.0/2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3; and LPDDR4/3/2 protocols. Also available, DesignWare Logic Libraries for TSMC 16FF+ processes include 7.5-, 9-, and...
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