Synopsys, Inc.
Mountain View, CA 94043
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Synopsys Accelerates Development of Safety-Critical Products with Design Solutions for ARM Cortex-R52
Synopsys Tools Enable Design and Safety Certification of Automotive, Industrial and Health Care SoCs Based on New ARMv8-R Architecture CPU MOUNTAIN VIEW, Calif. - Highlights: Galaxy Design Platform tools, including IC Compiler II place and route, Design Compiler Graphical synthesis, and ISO 26262-certified TetraMAX II ATPG enable optimal power, performance and area for ARM Cortex-R52 designs...
Read More »Synopsys Accelerates Development of Safety-Critical Products with Design Solutions for ARM Cortex-R52
Synopsys Tools Enable Design and Safety Certification of Automotive, Industrial and Health Care SoCs Based on New ARMv8-R Architecture CPU MOUNTAIN VIEW, Calif. - Highlights: Galaxy Design Platform tools, including IC Compiler II place and route, Design Compiler Graphical synthesis, and ISO 26262-certified TetraMAX II ATPG enable optimal power, performance and area for ARM Cortex-R52 designs...
Read More »Device Controller IP comply with DSI v1.2 and CSI-2 v1.2 specs.
Respectively supporting up to- 8 and 4 lanes of operation, DesignWare® MIPI® CSI-2SM Device Controller IP and DesignWare MIPI DSISM Device Controller IP let designers implement required camera and display functionality in mobile, automotive, and IoT applications. Both device controllers, interoperable with DesignWare MIPI D-PHY v1.2 operating at 2.5 Gbps/lane, offer integrated debug and...
Read More »Device Controller IP comply with DSI v1.2 and CSI-2 v1.2 specs.
Respectively supporting up toÃ- 8 andà4 lanes of operation, DesignWareî MIPIî CSI-2SM Device Controller IP and DesignWare MIPI DSISM Device Controller IP let designers implement required camera and display functionality in mobile, automotive, and IoT applications. Both device controllers, interoperable with DesignWare MIPI D-PHY v1.2 operating at 2.5 Gbps/lane, offer...
Read More »Synopsys TetraMAX II ATPG Certified for ISO 26262 Automotive Functional Safety
Independent Functional Safety Evaluation Provides Highest Level of Safety-Related Tool Confidence MOUNTAIN VIEW, Calif. - Highlights: Tool certification accelerates ISO 26262 functional safety qualification for automotive ICs up to the most stringent safety requirements for ASIL D Enables automotive IC design teams to accelerate their manufacturing test development process with 10X faster run...
Read More »Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs
New ATPG Engines Substantially Reduce Test Pattern Count for Lower Test Cost MOUNTAIN VIEW, Calif. - Highlights: Evaluation of TetraMAX II demonstrated an order of magnitude speedup in runtime Achieves significant test-pattern-count reduction without impacting test coverage Synopsys, Inc. (Nasdaq: SNPS), today announced that STMicroelectronics is seeing significantly faster test pattern...
Read More »Synopsys TetraMAX II ATPG Certified for ISO 26262 Automotive Functional Safety
Independent Functional Safety Evaluation Provides Highest Level of Safety-Related Tool Confidence MOUNTAIN VIEW, Calif. - Highlights: Tool certification accelerates ISO 26262 functional safety qualification for automotive ICs up to the most stringent safety requirements for ASIL D Enables automotive IC design teams to accelerate their manufacturing test development process with 10X faster run...
Read More »Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs
New ATPG Engines Substantially Reduce Test Pattern Count for Lower Test Cost MOUNTAIN VIEW, Calif. - Highlights: Evaluation of TetraMAX II demonstrated an order of magnitude speedup in runtime Achieves significant test-pattern-count reduction without impacting test coverage Synopsys, Inc. (Nasdaq: SNPS), today announced that STMicroelectronics is seeing significantly faster test pattern...
Read More »Test Pattern Generator cuts ATPG runtime from days to hours.
Built on test generation, fault simulation, and diagnosis engines that are extremely fast, TetraMAX-® II ensures patterns are ready when early silicon samples are first available for testing. Pattern reduction enables designers to shorten time of testing, while memory efficiency enables utilization of all server cores regardless of design size. Reuse of design modeling and rule checking...
Read More »Test Pattern Generator cuts ATPG runtime from days to hours.
Built on test generation, fault simulation, and diagnosis engines that are extremely fast, TetraMAXÃ-® II ensures patterns are ready when early silicon samples are first available for testing. Pattern reduction enables designers to shorten time of testing, while memory efficiency enables utilization of all server cores regardless of design size. Reuse of design modeling and rule checking...
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