Synopsys, Inc.
Mountain View, CA 94043
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Synopsys STAR Memory System Multi-Memory Bus Processor Enables 10 Percent Die Size Reduction for Marvell SoC
New Multi-Memory Bus Processor Cuts Test Logic in Half While Maintaining High Performance for Networking SoC MOUNTAIN VIEW, Calif. Highlights: • Marvell achieved silicon success for networking SoC using the multi-memory bus (MMB) processor in the Synopsys DesignWare STAR Memory System for embedded test and repair -- Reduced area and power with a single MMB processor providing common test and...
Read More »VIA Technologies Cuts Silicon Test Time by 11X Using Synopsys' DFTMAX Ultra
Standardizes on DFTMAX Ultra for Designs with Few Test Pins MOUNTAIN VIEW, Calif. Highlights: • DFTMAX™ Ultra compression technology deliver 11X higher compression and reduced test time • Higher test quality with shorter test time drove VIA's standardization on DFTMAX Ultra for pin-limited designs • Deployment of DFTMAX Ultra, built into Synopsys' Design Compiler-® RTL Synthesis...
Read More »Verification IP is available for Mobile PCIe technology.
Based on native SystemVerilog VIP architecture, VIP for M-PCIe™ technology enables enhanced performance, usability, and debugging in SystemVerilog UVM environments. Solution has built-in M-PHY-® and is integrated with Verdi-® Protocol Analyzer protocol-aware environment, which- offers simplified views of protocol traffic. Addition of M-PCIe technology to VIP for PCIe-® architecture- helps...
Read More »Synopsys' Galaxy Design Platform Delivers over 30% Leakage Power Reduction for Fujitsu Semiconductor's ARM-Powered Multi-Core
Power Savings Enabled by Unique Techniques and Design Flow Supported by Design Compiler Graphical, IC Compiler and PrimeTime Tools MOUNTAIN VIEW, Calif. — Highlights: - - - --- MB86S70 processor designed with ARM-® Mali™-T624 GPUs, ARM - - - - - - - Cortex-®-A15 and Cortex-A7 processors utilizing ARM big.LITTLE™ - - - - - - - processor configuration exceeds...
Read More »EDA Software Solutions support unified OCV extensions.
SiliconSmart-® library characterization, IC Compiler™ place and route, Library Compiler library checker and compiler, and PrimeTime-® ADV signoff- timing and noise analysis solutions support unified and standardized on-chip variation (OCV) extensions to open-source Liberty™ library format. Liberty Variation Format (LVF) extensions, including slew-load dependent transition and constraint...
Read More »TSMC and Synopsys Accelerate Custom Design Productivity for 16FF+ Process
Collaboration Enables Best Practices for Custom Implementation Productivity with FinFET Devices MOUNTAIN VIEW, Calif. – Highlights: - - - --- Synopsys custom design solution enhanced to meet emerging requirements - - - - - - - for 16FF+ process - - - --- Schematic and simulation environment enhanced to simplify - - - - - - - parasitic-aware circuit simulation...
Read More »ARM and Synopsys Expand Collaboration to Improve Quality of Results and Time-to-Results for Leading-Edge ARMv8-A and ARMv7-A Cores
Industry Leaders Sign Multi-year Subscription Agreement to Accelerate Design and Verification of ARM-based SoCs using Synopsys Tools CAMBRIDGE, United Kingdom and MOUNTAIN VIEW, Calif.- — Highlights: - - - --- Extended collaboration to benefit mutual customers with optimized - - - - - - - Synopsys implementation, verification and software development tools, - - - - - - - ...
Read More »Verification Software accelerates time-to-market for complex SoCs.
Verification Continuum is built from verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping, and debug in a unified environment with verification IP, planning, and coverage technology. Unified Compile with VCS and Unified Debug with Verdi, available- across verification flow, accelerate time-to-market by months for...
Read More »IC Compiler Software supports FinFET-based design.
Part of Synopsys' Galaxy™ Design Platform, IC Compiler™ 2014.09 utilizes look-ahead technologies, including accounting for downstream effects such as crosstalk at pre-route stage and performing virtual optimizations during placement. Program offers concurrent clock and data optimization, accelerated design closure using PrimeTime-® physically aware Engineering Change Order, and functions to...
Read More »Wipro Accelerates SoC Verification with Synopsys Verification IP Portfolio
Native SystemVerilog-based VIP Used in Advanced Testbench Methodology Environment to Address SoC Verification Challenges MOUNTAIN VIEW, Calif. - Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Wipro Ltd. has adopted Synopsys' broad portfolio of native SystemVerilog UVM-based...
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