Synopsys, Inc.
Mountain View, CA 94043
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Illumination Design Software models freeform optics.
With Advanced Design Module, LightTools-® v8.3 enables modeling of reflective and refractive freeform optics in both single-surface and segmented configurations for diverse set of illumination applications. Software also assists designers in modeling spatial temperature and power density variations in phosphor-based LEDs. API lets users develop custom volume scattering components, while Volume...
Read More »Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
Delivers Higher Frequency and Smaller Area Compared to Other Synthesis Solutions MOUNTAIN VIEW, Calif.- — Highlights: • Key ASIC has deployed Design Compiler Graphical to accelerate the design implementation of its consumer, wireless and personal electronics ICs • Comprehensive evaluation of available synthesis tools demonstrated Design Compiler Graphical's benefits of improved timing QoR...
Read More »Intel Custom Foundry Certifies Synopsys Implementation Tools for 14-nm FinFET Production
Galaxy Design Platform-based Implementation Flow Available Today for 14-nm MOUNTAIN VIEW, Calif. – Highlights: - - - --- Silicon-proven digital and custom implementation tools from the Galaxy - - - - - - - Design Platform are now certified for foundry customers on Intel's 14-nm - - - - - - - process - - - --- Silicon-proven Synopsys DesignWare IP is available for...
Read More »Power Controller/PHY IP Solution reduces mobile SoC energy draw.
Reducing active and standby power consumption for mobile SoCs, Synopsys DesignWare-® IP for PCIe-® 3.1 specification helps designers extend mobile device battery life. L1 sub-states and power gating techniques, including utilization of power switches, power islands, or retention cells, reduce standby power to
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Silicon-Proven IP offers 16 nm FinFET Plus processes.
DesignWare-® PHY IP for TSMC's 16 nm FinFET Plus processes (16FF+GL and 16FF+LL) enables designers to accelerate development of SoCs that incorporate embedded memories and interface IP for USB 3.0/2.0 and HSIC; PCIe-® 4.0/3.0/2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3; and LPDDR4/3/2 protocols. Also available, DesignWare Logic Libraries for TSMC 16FF+ processes include 7.5-, 9-, and 10.5-track...
Read More »TSMC Certifies Synopsys Design Tools for 16-nm FinFET Plus Production and for 10-nm Early Design Starts
Synopsys Tools are 16-nm-Certified and Deployed in Production Designs; 10-nm Co-development Enables Engagements with Early Adopters MOUNTAIN VIEW, Calif. - Highlights: - - - --- Certification includes the full suite of digital, signoff and custom - - - - - - - implementation tools - - - --- IC Compiler certification completed for 16-nm FinFET Plus v1.0 and the...
Read More »Automotive Lighting Design Software offers photorealistic images.
LucidShape-® v2.0 helps accelerate design development, verification, and delivery for automotive lighting engineers. By depicting all interactions between system geometry and light sources, included Visualize Module- delivers high-speed photorealistic images of automotive lighting system's lit appearance. Other features include Ray Data Viewer that creates ray data source-based illuminance...
Read More »Embedded Vision Processors are fully programmable, configurable.
DesignWare-® EV52 and EV54 implement- convolutional neural network (CNN) that can operate at >1,000 GOPS/W, accelerating accurate detection of such objects as faces, pedestrians, and hand gestures. To accelerate application software development, these vision processor IP cores are- supported by software programming environment based on existing and emerging embedded vision standards. Multiple...
Read More »Design Software accelerates development of ASIPs.
Using single input specification in nML language, ASIP Designer automatically generates synthesizable RTL of processor as well as SDK that includes optimizing C/C++ compiler, instruction set simulator, linker, assembler, software debugger, and profiler. Compiler generation technology includes LLVM compiler front-end and support for OpenCL kernel language. ASIP Designer also generates...
Read More »Verification IP enables audio and control interfaces.
Based on native SystemVerilog UVM architecture, Synopsys VIP for MIPI-® SoundWire enables IP, subsystem, and SoC designers to integrate designs and accelerate verification. SystemVerilog source code test suites eliminate tasks of developing verification environment and required tests. Complete with verification plans, built-in coverage, and support for protocol-aware debug, product accelerates...
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