Teledyne LeCroy Corporation
Chestnut Ridge, NY 10977
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New Protocol Analyzer and Exerciser Supports JEDEC UFS 3.1, MIPI UniPro v1.8 and M-PHY v4.1 HS-G4
Features Trace Validation™ artificial intelligence (AI) tool that uses complex state machine logic to analyze traces algorithmically. Offers SmartTuneTM equalization and eye monitor that help optimize signal acquisition at the analyzer to ensure error-free M-PHY symbol capture. Users can execute any loop order by speed, link widths, LUNs or individual test cases.
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New Protocol Analyzer and Exerciser Supports JEDEC UFS 3.1, MIPI UniPro v1.8 and M-PHY v4.1 HS-G4
Features Trace Validation™ artificial intelligence (AI) tool that uses complex state machine logic to analyze traces algorithmically. Offers SmartTuneTM equalization and eye monitor that help optimize signal acquisition at the analyzer to ensure error-free M-PHY symbol capture. Users can execute any loop order by speed, link widths, LUNs or individual test cases.
Read More »
Latest Protocol Analyzer is Designed to Capture PCIe 5.0 and CXL Traffic
Capable of capturing full x16 link width traffic at 32GT/s for the analysis of high-performance devices and systems. Can capture large traces to determine the root cause of any error or quickly identify performance degradation on the bus. Features hierarchical view of recorded traffic, real-time statistics, protocol traffic summaries, and detailed error reports.
Read More »
Latest Protocol Analyzer is Designed to Capture PCIe 5.0 and CXL Traffic
Capable of capturing full x16 link width traffic at 32GT/s for the analysis of high-performance devices and systems. Can capture large traces to determine the root cause of any error or quickly identify performance degradation on the bus. Features hierarchical view of recorded traffic, real-time statistics, protocol traffic summaries, and detailed error reports.
Read More »
New Summit Z516 Exerciser Simplifies Design Validation and Interoperability Stress Testing
Provides high performance 32 GT/s traffic generation on devices with link widths up to 16 lanes. Offers high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. Enables PCIe 5.0 device testing by generating flits on the flex bus within the link and transaction layers and supporting traffic generation and device/host emulation at all...
Read More »
New Summit Z516 Exerciser Simplifies Design Validation and Interoperability Stress Testing
Provides high performance 32 GT/s traffic generation on devices with link widths up to 16 lanes. Offers high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. Enables PCIe 5.0 device testing by generating flits on the flex bus within the link and transaction layers and supporting traffic generation and device/host emulation at all...
Read More »
New SierraNet M648 Protocol Test System with Net Protocol Suite Software Version 4.30
Analyzes PAM4 traffic over QSFP-DD and QSFP-56, as well as SFP connections. Fully tests their network capabilities and identifies issues that inhibit network efficiencies. Offers extensive and deep Ethernet protocol analysis.
Read More »
New SierraNet M648 Protocol Test System with Net Protocol Suite Software Version 4.30
Analyzes PAM4 traffic over QSFP-DD and QSFP-56, as well as SFP connections. Fully tests their network capabilities and identifies issues that inhibit network efficiencies. Offers extensive and deep Ethernet protocol analysis.
Read More »
New USB4, Thunderbolt 3 and 4 Exerciser Enable Users to Perform Testing for Next Generation Systems and Devices
Voyager M4x adds script-based traffic generation capabilities to mimic real-world USB4 device behaviors, allowing chip vendors to power up and fast test new silicon. Used in conjunction with the USB Implementers forum's command verifier application to generate traffic conditions required to verify responses for many of the official USB4 logical, protocol and tunneling layer tests. Users can...
Read More »
New USB4, Thunderbolt 3 and 4 Exerciser Enable Users to Perform Testing for Next Generation Systems and Devices
Voyager M4x adds script-based traffic generation capabilities to mimic real-world USB4 device behaviors, allowing chip vendors to power up and fast test new silicon. Used in conjunction with the USB Implementers forum's command verifier application to generate traffic conditions required to verify responses for many of the official USB4 logical, protocol and tunneling layer tests. Users can...
Read More »
New Protocol Analyzer and Exerciser Supports JEDEC UFS 3.1, MIPI UniPro v1.8 and M-PHY v4.1 HS-G4
Features Trace Validation™ artificial intelligence (AI) tool that uses complex state machine logic to analyze traces algorithmically. Offers SmartTuneTM equalization and eye monitor that help optimize signal acquisition at the analyzer to ensure error-free M-PHY symbol capture. Users can execute any loop order by speed, link widths, LUNs or individual test cases.
Read More »
New Protocol Analyzer and Exerciser Supports JEDEC UFS 3.1, MIPI UniPro v1.8 and M-PHY v4.1 HS-G4
Features Trace Validation™ artificial intelligence (AI) tool that uses complex state machine logic to analyze traces algorithmically. Offers SmartTuneTM equalization and eye monitor that help optimize signal acquisition at the analyzer to ensure error-free M-PHY symbol capture. Users can execute any loop order by speed, link widths, LUNs or individual test cases.
Read More »
Latest Protocol Analyzer is Designed to Capture PCIe 5.0 and CXL Traffic
Capable of capturing full x16 link width traffic at 32GT/s for the analysis of high-performance devices and systems. Can capture large traces to determine the root cause of any error or quickly identify performance degradation on the bus. Features hierarchical view of recorded traffic, real-time statistics, protocol traffic summaries, and detailed error reports.
Read More »
Latest Protocol Analyzer is Designed to Capture PCIe 5.0 and CXL Traffic
Capable of capturing full x16 link width traffic at 32GT/s for the analysis of high-performance devices and systems. Can capture large traces to determine the root cause of any error or quickly identify performance degradation on the bus. Features hierarchical view of recorded traffic, real-time statistics, protocol traffic summaries, and detailed error reports.
Read More »
New Summit Z516 Exerciser Simplifies Design Validation and Interoperability Stress Testing
Provides high performance 32 GT/s traffic generation on devices with link widths up to 16 lanes. Offers high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. Enables PCIe 5.0 device testing by generating flits on the flex bus within the link and transaction layers and supporting traffic generation and device/host emulation at all...
Read More »
New Summit Z516 Exerciser Simplifies Design Validation and Interoperability Stress Testing
Provides high performance 32 GT/s traffic generation on devices with link widths up to 16 lanes. Offers high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center performance. Enables PCIe 5.0 device testing by generating flits on the flex bus within the link and transaction layers and supporting traffic generation and device/host emulation at all...
Read More »
New SierraNet M648 Protocol Test System with Net Protocol Suite Software Version 4.30
Analyzes PAM4 traffic over QSFP-DD and QSFP-56, as well as SFP connections. Fully tests their network capabilities and identifies issues that inhibit network efficiencies. Offers extensive and deep Ethernet protocol analysis.
Read More »
New SierraNet M648 Protocol Test System with Net Protocol Suite Software Version 4.30
Analyzes PAM4 traffic over QSFP-DD and QSFP-56, as well as SFP connections. Fully tests their network capabilities and identifies issues that inhibit network efficiencies. Offers extensive and deep Ethernet protocol analysis.
Read More »
New USB4, Thunderbolt 3 and 4 Exerciser Enable Users to Perform Testing for Next Generation Systems and Devices
Voyager M4x adds script-based traffic generation capabilities to mimic real-world USB4 device behaviors, allowing chip vendors to power up and fast test new silicon. Used in conjunction with the USB Implementers forum's command verifier application to generate traffic conditions required to verify responses for many of the official USB4 logical, protocol and tunneling layer tests. Users can...
Read More »
New USB4, Thunderbolt 3 and 4 Exerciser Enable Users to Perform Testing for Next Generation Systems and Devices
Voyager M4x adds script-based traffic generation capabilities to mimic real-world USB4 device behaviors, allowing chip vendors to power up and fast test new silicon. Used in conjunction with the USB Implementers forum's command verifier application to generate traffic conditions required to verify responses for many of the official USB4 logical, protocol and tunneling layer tests. Users can...
Read More »