Hardent

New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

Supports VESA DSC 1.2a, a visually lossless video compression technology that increases the DisplayPort data transfer capacity by 3X using the same physical link speed. Includes Hardent VESA DisplayPort 1.4 Forward Error Corrector (FEC) TX or RX IP for Xilinx FPGAs. Transports UHD and HDR video streams for pro A/V applications such as digital signage, KVM extenders and switchers, high-end...

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New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

Supports VESA DSC 1.2a, a visually lossless video compression technology that increases the DisplayPort data transfer capacity by 3X using the same physical link speed. Includes Hardent VESA DisplayPort 1.4 Forward Error Corrector (FEC) TX or RX IP for Xilinx FPGAs. Transports UHD and HDR video streams for pro A/V applications such as digital signage, KVM extenders and switchers, high-end...

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New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X
Materials

New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X

VDC-M Encoder and Decoder IP Cores are designed for mobile phones, tablets, and AR/VR products and can be adopted in to MIPI Display Serial Interface℠ 2 v1.1 standards. Units support all VDC-M encoding/decoding mechanisms and use few transmission lanes compared to DSC. The cores offer a bitstream as low as 6 bits per pixel for HDR content and support up to ESA display compression-M standards.

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New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X
Materials

New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X

VDC-M Encoder and Decoder IP Cores are designed for mobile phones, tablets, and AR/VR products and can be adopted in to MIPI Display Serial Interface℠ 2 v1.1 standards. Units support all VDC-M encoding/decoding mechanisms and use few transmission lanes compared to DSC. The cores offer a bitstream as low as 6 bits per pixel for HDR content and support up to ESA display compression-M standards.

Read More »
New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

Supports VESA DSC 1.2a, a visually lossless video compression technology that increases the DisplayPort data transfer capacity by 3X using the same physical link speed. Includes Hardent VESA DisplayPort 1.4 Forward Error Corrector (FEC) TX or RX IP for Xilinx FPGAs. Transports UHD and HDR video streams for pro A/V applications such as digital signage, KVM extenders and switchers, high-end...

Read More »
New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

New Displayport 1.4 IP Subsystem Solution Meets the Requirements of Displayport Pro A/V Applications Transporting Video up to 8K

Supports VESA DSC 1.2a, a visually lossless video compression technology that increases the DisplayPort data transfer capacity by 3X using the same physical link speed. Includes Hardent VESA DisplayPort 1.4 Forward Error Corrector (FEC) TX or RX IP for Xilinx FPGAs. Transports UHD and HDR video streams for pro A/V applications such as digital signage, KVM extenders and switchers, high-end...

Read More »
New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X
Materials

New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X

VDC-M Encoder and Decoder IP Cores are designed for mobile phones, tablets, and AR/VR products and can be adopted in to MIPI Display Serial Interface℠ 2 v1.1 standards. Units support all VDC-M encoding/decoding mechanisms and use few transmission lanes compared to DSC. The cores offer a bitstream as low as 6 bits per pixel for HDR content and support up to ESA display compression-M standards.

Read More »
New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X
Materials

New VDC-M Encoder and Decoder IP Cores Offer Compression of up to 5X

VDC-M Encoder and Decoder IP Cores are designed for mobile phones, tablets, and AR/VR products and can be adopted in to MIPI Display Serial Interface℠ 2 v1.1 standards. Units support all VDC-M encoding/decoding mechanisms and use few transmission lanes compared to DSC. The cores offer a bitstream as low as 6 bits per pixel for HDR content and support up to ESA display compression-M standards.

Read More »

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