Kawasaki Microelectronics America, Inc.
San Jose, CA 95131
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K-micro to Sample World's First IEEE 1901 Fully Compliant Power Line Communication LSI Chip Set
Compliance enables high-performance, low-cost communications for devices that meet coexistence requirements of IEEE and ITU-T SAN JOSE, Calif. - K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, and a member of the HD-PLC Alliance, is announcing that it will be sampling the world's first chip set that is fully compliant with the IEEE 1901 standard (dubbed the KHN13100...
Read More »K-micro to Sample World's First IEEE 1901 Fully Compliant Power Line Communication LSI Chip Set
Compliance enables high-performance, low-cost communications for devices that meet coexistence requirements of IEEE and ITU-T SAN JOSE, Calif. - K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, and a member of the HD-PLC Alliance, is announcing that it will be sampling the world's first chip set that is fully compliant with the IEEE 1901 standard (dubbed the KHN13100...
Read More »Burst-Mode CDR SerDes targets XGPON1 OLT applications.
Available in 65 nm and 40 nm process technologies for ASIC integration, burst-mode CDR SerDes PHY chip can lock to upstream data burst at 2.488 Gbps in less than 16 bits. Device is also available as standalone chip for supporting reference designs. In addition, CDR SerDes can be configured to optimize burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gbps. With...
Read More »Burst-Mode CDR SerDes targets XGPON1 OLT applications.
Available in 65 nm and 40 nm process technologies for ASIC integration, burst-mode CDR SerDes PHY chip can lock to upstream data burst at 2.488 Gbps in less than 16 bits. Device is also available as standalone chip for supporting reference designs. In addition, CDR SerDes can be configured to optimize burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gbps. With...
Read More »PHY targets Ethernet Passive Optical Network applications.
Designed to meet IEEE802.3av standard, OLT SerDes PHY enables symmetrical operation at 10.3125 Gbps for downstream and upstream links. Built-in burst-mode BIST allows CDR to recover data bursts in less than 50 ns, even in high jitter. Unit's serial input port utilizes multivoltage-compatible CML interface, allowing it to be directly coupled to PMD device supporting interfaces from 0.5-3.3 V. It...
Read More »PHY targets Ethernet Passive Optical Network applications.
Designed to meet IEEE802.3av standard, OLT SerDes PHY enables symmetrical operation at 10.3125 Gbps for downstream and upstream links. Built-in burst-mode BIST allows CDR to recover data bursts in less than 50 ns, even in high jitter. Unit's serial input port utilizes multivoltage-compatible CML interface, allowing it to be directly coupled to PMD device supporting interfaces from 0.5-3.3 V. It...
Read More »Burst Mode CDR SerDes is suited for GPON OLTs.
Burst mode CDR SerDes PHY, supplied in 172-pin LBGA package, can be operated in automatic or manual mode and lock to upstream data burst at 1.244 Gbps in less than 20 bits. Using its transmit and receive parallel ports in TTL I/Os, product is suited for development of FPGA-based OLT reference designs. It is also available for multi-channel integration into ASICs and can be configured to improve...
Read More »Burst Mode CDR SerDes is suited for GPON OLTs.
Burst mode CDR SerDes PHY, supplied in 172-pin LBGA package, can be operated in automatic or manual mode and lock to upstream data burst at 1.244 Gbps in less than 20 bits. Using its transmit and receive parallel ports in TTL I/Os, product is suited for development of FPGA-based OLT reference designs. It is also available for multi-channel integration into ASICs and can be configured to improve...
Read More »FPGA Board enhance ASIC development and testing.
FPGA boards accelerate hardware and software development time associated with complex ASIC designs on CatsEye Development system. They are used to add logic to CatsEye chip platform, allowing full integration and testing of developers' IP before releasing design to fabrication. Connected to CatsEye Development system board via high-speed OCP inter-board connection, FPGA boards include Xilinx...
Read More »FPGA Board enhance ASIC development and testing.
FPGA boards accelerate hardware and software development time associated with complex ASIC designs on CatsEye Development system. They are used to add logic to CatsEye chip platform, allowing full integration and testing of developers' IP before releasing design to fabrication. Connected to CatsEye Development system board via high-speed OCP inter-board connection, FPGA boards include Xilinx...
Read More »K-micro to Sample World's First IEEE 1901 Fully Compliant Power Line Communication LSI Chip Set
Compliance enables high-performance, low-cost communications for devices that meet coexistence requirements of IEEE and ITU-T SAN JOSE, Calif. - K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, and a member of the HD-PLC Alliance, is announcing that it will be sampling the world's first chip set that is fully compliant with the IEEE 1901 standard (dubbed the KHN13100...
Read More »K-micro to Sample World's First IEEE 1901 Fully Compliant Power Line Communication LSI Chip Set
Compliance enables high-performance, low-cost communications for devices that meet coexistence requirements of IEEE and ITU-T SAN JOSE, Calif. - K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, and a member of the HD-PLC Alliance, is announcing that it will be sampling the world's first chip set that is fully compliant with the IEEE 1901 standard (dubbed the KHN13100...
Read More »Burst-Mode CDR SerDes targets XGPON1 OLT applications.
Available in 65 nm and 40 nm process technologies for ASIC integration, burst-mode CDR SerDes PHY chip can lock to upstream data burst at 2.488 Gbps in less than 16 bits. Device is also available as standalone chip for supporting reference designs. In addition, CDR SerDes can be configured to optimize burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gbps. With...
Read More »Burst-Mode CDR SerDes targets XGPON1 OLT applications.
Available in 65 nm and 40 nm process technologies for ASIC integration, burst-mode CDR SerDes PHY chip can lock to upstream data burst at 2.488 Gbps in less than 16 bits. Device is also available as standalone chip for supporting reference designs. In addition, CDR SerDes can be configured to optimize burst-mode lock time in OLT solutions for GPON standards operating at 1.25 Gbps. With...
Read More »PHY targets Ethernet Passive Optical Network applications.
Designed to meet IEEE802.3av standard, OLT SerDes PHY enables symmetrical operation at 10.3125 Gbps for downstream and upstream links. Built-in burst-mode BIST allows CDR to recover data bursts in less than 50 ns, even in high jitter. Unit's serial input port utilizes multivoltage-compatible CML interface, allowing it to be directly coupled to PMD device supporting interfaces from 0.5-3.3 V. It...
Read More »PHY targets Ethernet Passive Optical Network applications.
Designed to meet IEEE802.3av standard, OLT SerDes PHY enables symmetrical operation at 10.3125 Gbps for downstream and upstream links. Built-in burst-mode BIST allows CDR to recover data bursts in less than 50 ns, even in high jitter. Unit's serial input port utilizes multivoltage-compatible CML interface, allowing it to be directly coupled to PMD device supporting interfaces from 0.5-3.3 V. It...
Read More »Burst Mode CDR SerDes is suited for GPON OLTs.
Burst mode CDR SerDes PHY, supplied in 172-pin LBGA package, can be operated in automatic or manual mode and lock to upstream data burst at 1.244 Gbps in less than 20 bits. Using its transmit and receive parallel ports in TTL I/Os, product is suited for development of FPGA-based OLT reference designs. It is also available for multi-channel integration into ASICs and can be configured to improve...
Read More »Burst Mode CDR SerDes is suited for GPON OLTs.
Burst mode CDR SerDes PHY, supplied in 172-pin LBGA package, can be operated in automatic or manual mode and lock to upstream data burst at 1.244 Gbps in less than 20 bits. Using its transmit and receive parallel ports in TTL I/Os, product is suited for development of FPGA-based OLT reference designs. It is also available for multi-channel integration into ASICs and can be configured to improve...
Read More »FPGA Board enhance ASIC development and testing.
FPGA boards accelerate hardware and software development time associated with complex ASIC designs on CatsEye Development system. They are used to add logic to CatsEye chip platform, allowing full integration and testing of developers' IP before releasing design to fabrication. Connected to CatsEye Development system board via high-speed OCP inter-board connection, FPGA boards include Xilinx...
Read More »FPGA Board enhance ASIC development and testing.
FPGA boards accelerate hardware and software development time associated with complex ASIC designs on CatsEye Development system. They are used to add logic to CatsEye chip platform, allowing full integration and testing of developers' IP before releasing design to fabrication. Connected to CatsEye Development system board via high-speed OCP inter-board connection, FPGA boards include Xilinx...
Read More »