Aeluros, Inc.
Mountain View, CA 94043
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Integrated EDC/10G PHY/SerDes suits 10GBASE-LRM applications.
Supplied in 15 x 15 mm BGA or 10 x 10 mm packages, 10GbE PHY/SerDes devices feature integrated electronic dispersion compensation (EDC) for 10GBASE-LRM applications. Integrated products offers full PCS, PMA, and XGXS sub-layer functionality for XAUI-based optical modules and SFP+ systems applications. EDC algorithm addresses stress test pulses defined in IEEE 802.3aq specifications for...
Read More »Physical Layer Device suits 10GBASE-LRM applications.
Providing full implementation of IEEE 802.3ae 10 Gigabit Ethernet PHY layer functionality, Puma AEL1003 includes electronic dispersion compensation features to meet IEEE 802.3aq specification for 10GBASE-LRM. It has 4-lane 3.125 Gbps XAUI system-side interface, with 10G serial line-side interface appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules. Device includes PRBS...
Read More »LAN PHY and PHY/SerDes Devices come in pin compatible form.
Puma AEL1004 WIS-enabled 10GbE PHY/SerDes device incorporates on-board clock synthesizers that eliminate need for 2 clock sources for Ethernet and SONET/SDH rates; single clock input of 155.52 MHz drives SONET/SDH and Ethernet/XAUI clocking requirements. Puma AEL1006 LAN PHY device integrates VCSEL driver functionality as well as on-board clock synthesizer functionality, allowing Ethernet/XAUI...
Read More »Integrated EDC/10G PHY/SerDes suits 10GBASE-LRM applications.
Supplied in 15 x 15 mm BGA or 10 x 10 mm packages, 10GbE PHY/SerDes devices feature integrated electronic dispersion compensation (EDC) for 10GBASE-LRM applications. Integrated products offers full PCS, PMA, and XGXS sub-layer functionality for XAUI-based optical modules and SFP+ systems applications. EDC algorithm addresses stress test pulses defined in IEEE 802.3aq specifications for...
Read More »Physical Layer Device suits 10GBASE-LRM applications.
Providing full implementation of IEEE 802.3ae 10 Gigabit Ethernet PHY layer functionality, Puma AEL1003 includes electronic dispersion compensation features to meet IEEE 802.3aq specification for 10GBASE-LRM. It has 4-lane 3.125 Gbps XAUI system-side interface, with 10G serial line-side interface appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules. Device includes PRBS...
Read More »Aeluros Wins Challenging Line-Card Design With Its 10G LAN/WAN PHY
MOUNTAIN VIEW, Calif., Feb. 21 -- Aeluros, the leading supplier of low-power CMOS based 10G PHY solutions, today announced that High Performance Ethernet Switch Router vendor Force10 Networks has chosen Aeluros' 10G PHY devices for its next generation high-density 16-port 10GbE LAN/WAN PHY line card on its E1200 systems. These 2nd generation 10G PHY devices are pin compatible with Aeluros'...
Read More »LAN PHY and PHY/SerDes Devices come in pin compatible form.
Puma AEL1004 WIS-enabled 10GbE PHY/SerDes device incorporates on-board clock synthesizers that eliminate need for 2 clock sources for Ethernet and SONET/SDH rates; single clock input of 155.52 MHz drives SONET/SDH and Ethernet/XAUI clocking requirements. Puma AEL1006 LAN PHY device integrates VCSEL driver functionality as well as on-board clock synthesizer functionality, allowing Ethernet/XAUI...
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