NOR Flash Cell addresses wireless applications.
December 21, 2005 -
Suited for 1-bit/cell and 2-bit/cell products, 65 nm NOR Flash technology features cell size of 0.042 square microns. It utilizes cobalt salicide and 3 copper metallization layers to integrate NOR Flash array with low-voltage CMOS logic for 1.8 V applications.
Original Press release
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STMicroelectronics Unveils Smallest NOR Flash Cell at IEDM 2005
Industry-leading innovator presents its latest advances in Non-Volatile Memory and CMOS technologies
Geneva, December 5, 2005 - STMicroelectronics (NYSE: STM), one of the world's most innovative semiconductor companies, will participate as presenter or co-author of 13 papers at this year's International Electron Devices Meeting (IEDM) in Washington, DC, during December 5 - 7, 2005. ST's top-rank contributions include the world's first presentation of a 65 nm NOR Flash technology with the smallest cell size of 0.042 square micron and a novel HBT (Heterojunction Bipolar Transistor) architecture, enabling the development of low-cost, high-performance RF CMOS-based platforms for the most demanding applications.
"The scale and scope of our presence at this year's IEDM once again demonstrates ST's R&D strengths, its ability to spearhead innovation, and how ST drives the industrialization of leading-edge semiconductor technologies," said Laurent Bosson, Executive Vice President, Front-End Technology and Manufacturing at STMicroelectronics. "This demonstrably high level of research expertise is also testament to ST's ability to work in close cooperation with partners, including the Crolles2 Alliance and world-class research institutes from many countries."
Confirming its leadership in Non-Volatile Memories (NVM), ST will unveil a 65 nm NOR Flash technology with the smallest cell size of 0.042 square microns for high-performance 1-bit/cell and 2-bit/cell products. Addressing the critical requirements of today's wireless applications for higher Flash density and performance, ST's approach utilizes cobalt salicide and three copper metallization layers to integrate the 65 nm NOR Flash array with low-voltage CMOS logic for 1.8 V applications.
Paving the way towards cost-effective, high-performance RF-CMOS platforms, ST researchers in Crolles, France, have developed a low-cost SiGeC HBT (Heterojunction Bipolar Transistor) architecture for both bulk and SOI substrates. The new device can be fabricated by adding only four masks to the core CMOS and its novel fragmented emitter layout minimizes the resistance of an all-implanted collector.
The high number of ST papers at IEDM 2005 is complemented with an opening Plenary Talk, to be given by ST's Benedetto Vigna, Director of the MEMS Business Unit, which outlines the Company's perspective on MEMS technologies, products, and applications. ST experts were also invited to participate in the discussion panels on the future of Non-Volatile Memories and Semiconductor R&D.
Micro-electro-mechanical (MEMS) devices are penetrating an ever wider array of applications in automotive, industrial, computer, and consumer markets. At the forefront of the MEMS research and industrialization, ST's plenary presentation identifies new markets and applications, such as wireless sensor networks, smart pills, and Labs-on-Chips, that will benefit from small-size, low-power, and inexpensive micro-machined mechanical structures on a silicon substrate.
Phase Change Memory (PCM) technology attracts increasing attention as a leading candidate for the next generation of non-volatile memories. Two papers from ST's research center in Agrate, Italy, in cooperation with the Polytechnic of Milan, study mechanisms in amorphous chalcogenide materials that constitute PCM cells, explaining their recovery dynamics and impacts of crystallization on data retention.
Another two contributions deal with the important aspects of scaling and reliability in Non-Volatile Memory structures. A paper co-authored by research partners at the Polytechnic of Milan, reveals a new experimental technique for investigating stress-induced defects in the silicon oxide, while the second paper, co-authored by ST, CEA-LETI, the University of Pisa, and CNRS, describes a study of electrical behavior in discrete-trap Non-Volatile Memories during data retention and its impact on cell-scaling.
ST Crolles, together with CEA-LETI and other research partners, will present a paper on the fabrication of ultra-short channel strained-Ge pMOSFETs for high-performance dual-channel CMOS. Experimental results demonstrate an unparalleled enhancement in hole mobility gains with a thin high-k gate dielectric, achieved by optimization of the strained Si and Ge heterostructure.
A paper on the convergence of silicon CMOS and MEMS technologies describes the suspended-gate MOSFET as a candidate architecture for an integrated current switch with a record sub-threshold slope of 2mV/decade and ultra-low gate leakage.
Together with Philips and Freescale, ST will co-present at IEDM 2005 the latest achievements of the joint research teams working within the Crolles2 Alliance. These include first operational SRAM cells featuring NiSi Totally Silicided (TOSI) gates on a state-of-the-art industrial CMOS technology; an enhanced Trench First Hard Mask (TFHM) backend architecture for the integration of advanced low-k dielectric films on the 65 nm technology node and below; a demonstration of curing effects of T>475° C anneals on charging damages in Hf-based materials; and the potential of Laser Spike Annealing (LSA) for the CMOS scaling, enabling the effective integration of the 30 nm device in a 45 nm bulk CMOS platform.
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2004, the Company's net revenues were $8.76 billion and net earnings were $601 million. Further information on ST can be found at www.st.com.