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EDA Software cuts die-package interconnect planning time.

May 30, 2014 - Used early in design cycle, Cadence® OrbitIO™ provides rapid planning of interfaces across multiple fabrics. As part of overall co-design solution, Cadence OrbitIO integrates with Cadence SiP Layout and Cadence Encounter® digital implementation platform, allowing design teams to clearly communicate design intent throughout flow. Software can enable fabless semiconductor or systems companies to evaluate package route feasibility, and communicate route plan to package design resources.
Original Press release

Cadence Design Systems, Inc.
2655 Seely Ave.
San Jose, CA, 95134
USA


Cadence Announces New Integrated Solution for Rapid Die-Package Interconnect Planning


Enables concurrent optimization of multi-fabric elements, leading to lower cost and higher performance



SAN JOSE, Calif.,  -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced a new integrated solution to significantly cut down die-package interconnect planning time from weeks to days by reducing iterations between silicon and package design teams. The solution, built on Cadence(®) OrbitIO(TM) technology, also shortens the time to converge on the physical interface between the die and package up to 60 percent, all within the context of the full system.



Building on its leadership position for co-design in the implementation stage, Cadence OrbitIO technology is used earlier in the design cycle to provide rapid interconnect planning of high-performance interfaces across multiple fabrics. As part of an overall co-design solution, Cadence OrbitIO technology provides seamless integration with Cadence SiP Layout and the Cadence Encounter® digital implementation platform. This integrated solution allows design teams to clearly communicate design intent throughout the flow, resulting in better decision-making, fewer iterations and shorter cycle-times. It can enable fabless semiconductor or systems companies to evaluate package route feasibility, and allows them to communicate a route plan to their package design resources, whether it is to an internal group or to an outsourced assembly and test (OSAT) provider.



"The Cadence OrbitIO global view of system connectivity helps Faraday reduce the time required to converge on the optimal die bump to package ball pad assignment," said Dr. Wang-Jin Chen, senior technologist of Faraday. "The combination of connectivity optimization and route feasibility functions helped us produce a route plan resulting in two fewer package layers with all DDR signals implemented on a single package layer."



To learn more about OrbitIO technology, please visit: www.cadence.com/products/sigrity/orbitio/pages/default.aspx



About Cadence

Cadence  (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.



© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Encounter are registered trademarks of, and OrbitIO is a trademark of, Cadence Design Systems, Inc. in the United States and other countries.



For more information, please contact:

Cadence Newsroom

408-944-7039

newsroom@cadence.com



Web Site: http://www.cadence.com
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