Verification IP optimizes FPGA and SoC design reliability.
Press Release Summary:
Supporting FPGA and SoC designs based on ARM AMBA 4 architecture, plug-and-play AXI4 Verification IP was developed in SystemVerilog and is available for OVM, VMM, and UVM verification methodologies. Reusable, configurable, and pre-verified, AXI4 VIP supports functional coverage for checkers to ensure IP/RTL behavior is continuously monitored. For faster debug cycles, solution includes features such as Transaction Tracker and Bandwidth Monitor.
Original Press Release:
New AXI4 VIP Suite to Improve FPGA and SoC Reliability for ARM®-based Designs
eInfochips to Enable Companies Using the Popular ARM Architecture With AMBA(R) 4 AXI4 Verification IP
SUNNYVALE, California -- eInfochips, a leading Product Engineering Services provider has announced the availability of the AXI4 Verification IP
[ https://www.einfochips.com/index.php/solutions/verification-ips/axi.html (VIP) to improve reliability of FPGA and SoC designs based on the popular ARM AMBA 4 architecture. The solution already supports AXI4 and AXI4-Lite, and will have AXI4-Stream variant available in Q1 FY16. It is ideal for companies that design complex, high-performance devices, to ensure robust standards-compliant AXI4 implementation. The eInfochips AXI4 VIP is a plug-and-play solution developed in SystemVerilog, and is available for OVM, VMM and UVM verification methodologies.
Parag Mehta, the Chief Marketing and Business Development Officer at eInfochips said, "Reliability is non-negotiable in the semiconductor industry, and so is time-to-market. We are key enablers for both these parameters for leading global corporations. Our VIPs, combined with our verification, implementation and DFT services have enabled more than 150 tape-outs already."
ARM AMBA-based AXI4 Protocol and AXI4 VIP
AXI4 is an AMBA-based protocol designed specifically for high bandwidth and low latency performance. It is majorly deployed as a system interface in a majority of networking, storage, computing, consumer and IoT applications. The eInfochips AXI4 VIP supports functional coverage for checkers to ensure the IP/RTL behaviour is continuously monitored. For faster debug cycles, eInfochips AXI4 VIP has features such as TRANSACTION TRACKER and BANDWIDTH MONITOR.
The eInfochips AXI4 VIP can be introduced to an existing verification environment as a retrofit, given that it is designed with SystemVerilog and supports OVM, VMM and UVM. The complete feature set and specifications data sheet can be found here [ https://www.einfochips.com/images/solutions/Datasheet-AXI_4.0.pdf .
Custom VIP Development Services
eInfochips has developed more than 32 VIPs for the world's leading EDA tools, as well as other companies. The team has hands-on design experience on VIPs for key protocol standards like MIPI [ https://www.einfochips.com/index.php/solutions/verification-ips/mipi-rffe-1-0-vip.html , USB3.0, DDR3, HDMI and eMMC [ https://www.einfochips.com/index.php/solutions/verification-ips/emmc-5-0.html . VIPs designed by eInfochips power the development of hundreds of ASIC, SOC and FPGA devices.
About eInfochips
eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.
Visit us at www.einfochips.com [ http://www.einfochips.com , or stay connected on LinkedIn [ http://www.linkedin.com/company/einfochips , Facebook [ https://www.facebook.com/eInfochips , SlideShare [ http://www.slideshare.net/eInfochips_Solution , Twitter [ https://twitter.com/einfochipsltd and YouTube [ http://www.youtube.com/user/einfochipsindia?feature=watch .
To request information, contact:
Mayank Shukla
(+1) 408-496-1882Â
(+91) 79-2656-3705
marketing@einfochips.com
