Verification Solution ensures proper PLL operation.
May 17, 2006 -
GoldenGate offers transistor-level, phase-locked loop solution for verifying complete closed loop noise and jitter, allowing designers to verify designs prior to silicon. Viewing full noise contributions from all contributors, including crystal oscillator, enables designers to pinpoint and fix problems prior to tape-out.
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|Original Press release |
Xpedion Design Systems
1900 McCarthy Blvd., Suite 210
Milpitas, CA, 95035
Xpedion Design Systems Introduces Industry's First Transistor-Level Closed Loop PLL Verification Solution
Milpitas, California (USA) - April 25, 2006 - Xpedion Design Systems, Inc., a provider of next generation RFIC and PLL simulation and verification, today announced the industry's first transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter. This breakthrough allows PLL designers to fully verify their designs prior to silicon to save design spins and reduce time to production.
Phase-locked loops are present in a majority of complex integrated circuits produced today in applications ranging from microprocessors to wireless communications. They also represent one of the most challenging design hurdles to overcome and are often the reason for failing silicon. The capability of GoldenGate to accurately ensure proper PLL operation is an industry breakthrough. Xpedion has developed this technology in conjunction with close partners and has validated through measured silicon.
"We worked with Xpedion to successfully verify simulated results against measured data for our CMOS PLL with over 500 transistors operating at 622 Mhz, including the crystal oscillator and the integer divider," states Pierre Guebels, Vice President of Engineering at Phaselink Corporation. "This capability is a tremendous step forward in successfully verifying PLLs prior to tape-out."
This capability takes advantage of Xpedion's leadership in harmonic-balance capacity, simulation speed and phase-noise analysis. GoldenGate allows designers to view full noise contributions from all contributors, including the crystal oscillator, allowing designers to pinpoint and fix problems. Historically, this is done through an iterative process of respins.
"We are able to address a clear need in the industry to verify proper PLL operation through our advanced capabilities," says George Estep, Director of Applications Engineering at Xpedion. "This capability will save our customers painful design iterations allowing them to get their products to market faster."
Currently, Xpedion is engaging with existing customers on this technology through partnerships and service agreements. For more information, please contact your local Xpedion support.
About Xpedion Design Systems
Xpedion delivers the most advanced RFIC simulation technology, GoldenGate, in the industry. This enables RFIC designers to analyze their designs at the transistor level faster and more accurately. The benefits are measured in shorter design cycles, reduced silicon spins and higher performing products. Xpedion is a member of the Ready for IBM Technology Program, Cadence Connections Program, the Mathworks Connections Program, the Platform Partners Program, and is a Sun Microsystems development partner. Xpedion's products are also available on the Red Hat Linux operating system. Xpedion Design Systems, Inc. is located at 1900 McCarthy Blvd., Suite 210, Milpitas, California, USA, 95035. Telephone: (408) 449-4000, FAX: (408) 449-4030, email: firstname.lastname@example.org, Internet: www.xpedion.com.
Xpedion Company Contact:
Mr. Pete Johnson
Tel: (408) 449-4022