VLIW 8-MAC DSP Core accelerates data throughput.June 11, 2010 -
Intended for SoC designs, ConnX 545CK dataplane processor core combines base CPU controller with DSP that can sustain 8 simultaneous MAC (multiply-accumulate) operations on independent data pairs per cycle utilizing 160-bit vector registers. It features 3-issue VLIW (very long instruction word) architecture with eight 16-bit multipliers that operate in SIMD mode. Capable of 600+ MHz operation, core also has two 128-bit load/store units and Viterbi convolutional coder accelerator.
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Original Press release
Tensilica, Inc.
3255-6 Scott Blvd.
Santa Clara, CA, 95054
USA
Tensilica Introduces Third Generation ConnX 545CK 8-MAC VLIW DSP Core
Updated ConnX 545CK Features 20% Faster Speed, 30% Lower Power and 10% Smaller Size
SANTA CLARA, Calif. - Tensilica, Inc. today introduced its third generation ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. Improvements in this third generation dataplane processor (DPU) core deliver up to 20 percent faster clock speed, 11 percent smaller die and up to 30 percent lower power consumption.
The ConnX 545CK is ideal for SOC dataplane signal processing because it allows system control and high-speed signal processing throughput in a single core with a single compiler and single instruction stream. It combines a base CPU controller with a DSP that can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.
"The seamless blending of traditional CPU and traditional DSP characteristics makes all of Tensilica's ConnX brand DPUs uniquely well suited to a variety of wired and wireless communications applications," stated Steve Roddy, Tensilica's vice president of marketing and business development. "The ConnX 545CK is a ready-to-use, off-the-shelf octal- MAC solution. And for designers seeking to tailor a DSP further, the ConnX 545CK can be augmented to perfectly suit a particular target application by utilizing the unique customization capabilities of Tensilica's Xtensa LX3 processor."
The ConnX 545CK features a 3-issue VLIW architecture with eight 16-bit multipliers that operate in SIMD (single instruction, multiple data) mode. The core can sustain eight parallel multiply-accumulate operations per cycle. The compiler automatically vectorizes code to take maximum advantage of the architecture. It also has two 128-bit load/store units and a built-in Viterbi convolutional coder accelerator.
One of the unique features of the ConnX 545CK is the 32-bit input/output Queue interfaces that function like FIFOs (first in, first out), to bypass the system bus and communicate directly to streaming data interfaces. This allows much faster data throughput than traditional DSPs, which require memory-based load and store operations on each data element.
Availability
The ConnX 545CK Revision C is available now. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation.
About Tensilica
Tensilica, Inc. is the leader in customizable dataplane processors IP cores. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific signal processing performance targets. Tensilica's DPUs power SOC designs at system OEMs and six out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes, digital still cameras and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.
Notes:
Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names mentioned are trademarks and/or registered trademarks of their respective owners.
Tensilica's announced licensees include: ADDMM, Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Blue Wonder, Brocade, Broadcom, Cisco Systems, CMC Microsystems, Conexant Systems, Design Art Networks, DS2, EE Solutions, Epson, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Fujitsu Microelectronics Ltd., the HiSilicon division of Huawei, Hudson Soft, iBiquity Digital, Ikanos Communications, IDT, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, NEC Laboratories America, NEC Corporation, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Panasonic Mobile, Penstar, Plato Networks, PnpNetwork Technologies, PowerLayer Microsystems, Samsung, SiBEAM, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, Triductor Technology, UpZide, Valens Semiconductor, Validity Sensors, Victor Company of Japan (JVC), WiLinx, and XM Radio.
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