Processor Core is used for portable multimedia applications.November 14, 2006 -
Compliant with CEVA-X Instruction Set Architecture, Model CEVA-X1641(TM) fully synthesizable core enables users to configure optimal memory size and structure for applications such as WiMAX and WiBro. Product offers 4 MAC units operating in parallel coupled with 128-bit data memory bandwidth. Digital signal processor (DSP) core features combined VLIW/SIMD architecture and incorporates video instructions and mechanisms to enable multimedia processing.
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Original Press release
CEVA, Inc.
2033 Gateway Place
San Jose, CA, 95110-3710
USA
CEVA Debuts CEVA-X1641 - High-Performance Quad-MAC DSP Targeting Next-Generation Cellular and Portable Multimedia Applications
Upwardly Code Compatible With Existing CEVA-X Family Members, CEVA-X1641 Protects Customers' Software Investment, Speeds Time-to-Market and Reduces Development Risk for a Range of Applications
SAN JOSE, Calif., Oct. 30 -- CEVA, Inc. (NASDAQ:CEVA), the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry, today announced the CEVA-X1641(TM) -- the newest addition to the company's industry-proven family of CEVA-X DSP cores and fully compliant with the CEVA-X Instruction Set Architecture (ISA).
CEVA-X1641 is the first Quad-MAC DSP core in the scalable CEVA-X family and is designed specifically to run highly computational intensive tasks that require substantial data throughput and high memory bandwidth. The core is fully synthesizable with enhanced memory architecture. This provides customers with the flexibility to configure the optimal memory size and structure for their specific application such as WiMAX, WiBro, 3G Long Term Evolution (LTE), or advanced multimedia standards, including the evolving H.264 compression standard and VC1 main profile. In defining the CEVA-X1641, CEVA worked closely with a lead customer that chose to utilize the CEVA-X-1641 for its WiMAX product line.
Like other CEVA-X ISA compliant cores, CEVA's latest DSP core is a combined VLIW/SIMD architecture, with additional features and enhancements required to handle the high-performance and data-throughput requirements of 4G technologies and multimedia applications. Highly computational intensive technologies such as WiMAX are calling for the use of 4 MAC units, coupled with a 128bit data memory bandwidth, to handle the extremely high data rates capable of reaching 100Mbps. Furthermore, CEVA-X1641 incorporates specialized video instructions and mechanisms to accelerate multimedia processing in applications like mobile TV and video conferencing, while reducing frequency and power consumption to extend the battery life of these fully featured mobile multimedia devices.
"The CEVA-X1641 DSP core is in line with our strategy to offer platforms that will support the growing need for performance and power-efficient DSPs for emerging wireless and multimedia standards," said Gideon Wertheizer, CEO of CEVA, Inc. "Our new, high-performance and fully synthesizable CEVA-X1641 DSP core will enable customers to expedite their time-to-market and reduce development costs by using the same platform across multiple, differentiated products."
The CEVA-X1641 is upward compatible with CEVA-X1620(TM) and CEVA-X1622(TM) DSP cores, enabling licensees of the CEVA-X1641 to leverage the broad range of software and components already available for the CEVA-X architecture. In addition, the CEVA-X1641 architecture is implemented in a small size, only 5 percent larger than its Dual- MAC predecessor, the CEVA-X1620.
Delivering on the promise of the scalable CEVA-X family introduced in 2003, the CEVA-X1641's main features are:
o 4-MAC units operating in parallel
o 8 issue VLIW
o 24 40bit accumulators
o 128bit data bandwidth
o 8/16/32/40bit data operands and operations
o 16/32bit instructions
The VLIW architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption. SIMD architecture allows single instructions to operate on multiple data elements that result in code size reduction and increased performance. Low power consumption is achieved in the CEVA-X1641 by its efficient instructions and dedicated mechanisms such as dynamic and selective unit shutdowns and clock gating.
The CEVA-X1641 provides a high-performance, low-power platform allowing its licensees to develop multi-mode products (e.g., 2G/3G/4G processors) and to reuse the same platform for next-generation standards such as 802.16e, WiBro, Flash-OFDM, UMTS and TD-SCDMA.
The CEVA-X1641, together with a complete software development tool chain, is available for immediate licensing.
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including multimedia, audio, Voice over Packet (VoP), Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2005, CEVA's IP was shipped in over 130 million devices. For more information, visit www.ceva-dsp.com .
Source: CEVA, Inc.
CONTACT:
Richard Kingston of CEVA, Inc.,
+1-408-514-2976,
richard.kingston@ceva-dsp.com
Web site: http://www.ceva-dsp.com/
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