Memory Controller and PHY IP fully support DDR3 DIMMs.
June 5, 2008 -
Databahn(TM) DRAM memory controller and hard PHY IP offer full DDR3 dual in-line memory module (DIMM) support. They are designed for bulk-memory and caching applications, including networking, storage, and personal computing systems using DDR3 modules at data rates up to 12.8 GB/sec per DIMM. Utilizing fly-by architecture, products require read and write leveling and gate training capabilities to be directly implemented and managed in DRAM controller and PHY.
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
|Original Press release |
Denali Software Inc.
644 Emerson St., Suite 7
Palo Alto, CA, 94301
Denali First to Release Full DDR3 DIMM IP Solution
Sole Provider of Memory Controller and Hard PHY Solution to support both DDR3 chips and modules for Networking, Storage, and Personal Computing
SUNNYVALE, Calif., May 29 -- Denali, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced the immediate availability of its Databahn(TM) DRAM memory controller and hard PHY IP with full DDR3 dual in-line memory module (DIMM) support designed for bulk-memory and caching applications, including networking, storage and personal computing. Denali announced embedded systems support for discrete DDR3 DRAM chips last year as memory vendors began offering new devices to support data rates up to 1600Mbit/s per pin. This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.
"The DDR3 DIMM is a high-volume product used by SoC customers who require a large amount of high-bandwidth memory," remarked Brian Gardner, vice president of IP products at Denali Software. "To achieve this higher bandwidth, DDR3 DIMMs utilize a 'fly-by' architecture which requires read and write leveling and gate training capabilities to be directly implemented and managed in both the DRAM controller and the PHY. Our customers look to Denali to provide high-quality, interoperable, and configurable IP that supports the DDR3 DRAM architecture where DIMM concepts can be applied."
About Databahn Solutions
Denali's Databahn DDR DRAM solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, and LP-DDR devices from all major memory vendors and all vendor process nodes. Deliverables include: RTL and synthesis scripts, choice of silicon-independent DDR Soft PHY or silicon- specific DDR Hardened PHY with all common views, verification test bench, static timing analysis (STA) scripts, programmable register settings, documentation, I/O pads and packaging. Databahn controllers are compliant with all the latest memory devices. For more information about Databahn DDR DRAM solutions, visit: http://denali.com/dram.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to- market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at denali.com.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.