HEVC Decoder Silicon IP features 10 bit support.
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Press Release Summary:
Supporting both Main and Main 10 profiles, HEVC Decoding IP is based on scalable multi-core architecture, supporting any combination of parallel processing tools, including dependent slices, tiles, and wavefront parallel processing. Decoder architecture removes all constraints on encoders and ensures interoperability with all types of parallelized encoding. Running real-time on FPGA, HEVC Decoding IP is suited for any customer requiring 4K enabled products.
Original Press Release:
Allegro DVT Improves Its HEVC Decoder Silicon IP with 10 Bit Support
GRENOBLE, France – Developed to compress 4K and high resolution video contents, the next generation video standard: HEVC/H.265 brings fifty percent bitrate saving compared to content encoded with H.264/AVC.
Requirement of TV broadcasting for carrying 4K and ultra-high definition content is now driving the adoption of the HEVC (High Efficiency Video Coding) standard.
This demand for devices supporting HEVC is growing fast, and Allegro DVT is ready with the industry's first fully compliant HEVC decoding IP that supports both Main and Main10 profiles. The Main10 profile was specifically designed to improve 4K content video quality thanks to 10 bit color depth support.
Our HEVC Decoding IP is available today, runs real-time on FPGA and can be immediately delivered to any customer wishing for 4K enabled products. We see that 4K content will drive the market of next-generation ultra HD television displays (UHDTV) and content capture systems. Our customers have an immediate requirement for HEVC into System on Chip (SoC), which we are ready to address with our HEVC Decoding IP.
One of the major innovations in the HEVC standard, is the introduction of several tools to parallelize processing, such as "dependent slices", "tiles" and "wavefront parallel processing". Our HEVC Decoding IP is based on a scalable and unique multi-core architecture, supporting any combination of these parallel processing tools. This unique decoder architecture removes all constraints on the encoders and ensures interoperability with all types of parallelized encoding.
The HEVC Decoding IP core is designed to be easily integrated in all next generation SoC devices requiring exceptional performance while maintaining a very low operating frequency and high level of power savings.
Allegro DVT is a leading provider of H.264/MPEG-4 AVC|SVC|MVC and HEVC/H.265 solutions, including industry standard compliance test suites, H.264/MPEG-4 AVC and HEVC/H.265 encoder, codec and decoder silicon (RTL) IPs; and multiscreen encoders and transcoders. Allegro DVT products have been chosen by more than 100 major IC providers, OEMs and broadcasters.
For more information, visit Allegro DVT's Website (http://www.allegrodvt.com/Allegro).
CONTACT: For information or a live demonstration of our HEVC Decoder IP, please contact us at info@allegrodvt.com. Phone: +33-4-76-42-66-85 ext. 011
