Gigabit Ethernet IP Cores reduce design complexity.
July 17, 2012 -
Used for building systems requiring high-throughput standard Ethernet connections, 40 and 100 GbE IP cores create high-performance subsystem IP in 40 nm Stratix IV and 28 nm Stratix V FPGAs. MAC and PCS+PMA sublayer IP cores are IEEE 802.3ba(TM)-2010 standard compliant and optimized for integration with Altera development kits and Quartus® II software v12.0. Interface is composed of single packet-based channel that is logically compatible with previous-generation Ethernet systems.
Original Press release
Altera Corporation
101 Innovation Drive
San Jose, CA, 95134
USA
Altera Reduces Design Complexity in High-Performance 40GbE/100GbE Designs with Latest IP Core Offering
40GbE/100GbE IP Provides a Complete Solution for Customers Integrating Ethernet Into FPGA-Based Systems
SAN JOSE, Calif. -- Altera Corporation (NASDAQ: ALTR) today announced the production availability of its 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores. These cores are effective for building systems requiring very high throughput-rate standard Ethernet connections, including chip-to-optical module, chip-to-chip, and backplane applications. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba(TM)-2010 standard compliant, reducing design complexity for customers integrating 40GbE and 100GbE connections on Altera's 28-nm Stratix® V FPGAs and 40-nm Stratix IV FPGAs.
"As more system designs use Ethernet at high speeds--not only for local-area network attachment but to interconnect within systems--subsystem IP, including 40GbE/100GbE MAC and PCS+PMA layers, becomes a vital component in the system design team's toolkit," said Vince Hu, vice president of corporate and product marketing. "These cores, optimized for integration with Altera development kits and Altera's Quartus® II software v12.0, create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs."
With this development, Altera is enabling the system-level throughput promise of 40GbE/100GbE and raising the level of design abstraction for FPGA designers, while boosting design team productivity. The 40GbE and 100GbE MAC and PHY IP cores provide an interface composed of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera's Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05 Gbps and 14.1 Gbps, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3 Gbps. Stratix FPGAs combine high density, high performance and a rich feature set, allowing customers to integrate more functions and maximize system bandwidth.
Pricing and Availability
Altera's 40GbE and 100GbE IP cores are available for separate download from Altera.com and are compatible with the recently announced Quartus II software v12.0. For more information on Altera's 40GbE and 100GbE IP cores, please visit www.altera.com/40-100GbE. For pricing information, please contact sales@altera.com.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal.
|
|
|
|
|
|
|
|
