Field Programmable Gate Array supports DDR3 DIMM modules.September 4, 2007 -
Featuring 150K logic elements, EP3SL150 is 65 nm Stratix® III FPGA that complies with JEDEC DDR3 SDRAM standard, including read and write leveling to DIMMs as well as devices. I/O blocks are embedded with all timing-critical circuits, and Programmable Power Technology enables every programmable logic array block, DSP block, and memory block to operate independently at high-speed or low-power mode, automatically controlled via PowerPlay feature in Quartus II software.
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
Original Press release
Altera Corporation
101 Innovation Drive
San Jose, CA, 95134
USA
Altera Ships First Member of High-End Stratix III FPGA Family
Industry's Lowest-Power High-Performance FPGAs Offer 25 Percent Performance Advantage Over Competing Solutions
SAN JOSE, Calif., Aug. 28 -- Altera Corporation (NASDAQ:ALTR) today announced the shipment of the EP3SL150, the first member of its 65-nm Stratix(R) III FPGA family. Featuring 150K logic elements and delivering the lowest power consumption of any high-density, high-performance programmable logic device, the EP3SL150 is ideal for a broad range of applications such as high performance computing, next-generation basestations, network infrastructure, and advanced imaging equipment.
"We chose the Stratix III family for its clear performance advantages and significant power savings," said Thomas Stubitsch, chief architect at XtremeData. "Some of our customers are asking for maximum logic density, while others are asking for the highest double precision floating point performance. The Stratix III 'L' and 'E' families allow us to offer both."
Stratix III FPGAs offer both 45 percent lower power consumption and a 25 percent performance advantage over competing solutions. The combination of Stratix III FPGAs and Altera(R) Quartus(R) II design software improves productivity as well as performance. For example, in the area of memory interfaces, the Stratix III FPGAs provide designers with the industry's only fully compliant interface support for the newly ratified JEDEC DDR3 SDRAM standard, including read and write leveling to DIMMs as well as devices.
"We see DDR3 becoming the memory solution of choice for next-generation systems requiring high bandwidth," said Raymond Fontayne, segment marketing manager at Micron Technology, Inc. "We are pleased to see that Altera's Stratix III FPGAs provide built-in read-and-write leveling functionality required to allow operation with our DDR3 SDRAM DIMMs and devices."
"We chose Altera's Stratix III series of FPGAs for interfacing with DDR3 DIMM modules because the built-in read/write leveling in the I/O blocks in Stratix III FPGAs are a key system design feature that significantly simplifies design and enables the highest system performance," said Sunny Chang, president and chief operating officer at KINGTIGER Technology (Canada) Inc. "By engaging with Altera through their early access program they have provided a highly efficient reference design and timely technical support that has ensured design success."
"Altera's Stratix III series of FPGAs are the industry's only programmable logic devices supporting DDR3 DIMM modules," said Bill Chan, president, Triad Spectrum. "Because Stratix III I/O blocks are embedded with all the timing-critical circuits, we are very confident of hitting performance targets far beyond 800 Mbps. My design team is working closely with Altera to ensure our successful design."
To dramatically lower power while simultaneously delivering high performance, Stratix III FPGAs feature Altera's innovative Programmable Power Technology. This power management technology enables every programmable logic array block (LAB), digital signal processing (DSP) block and memory block to operate independently at high-speed or low-power mode. The PowerPlay feature in Quartus II software automatically controls the mode of each block based on performance requirements. Another unique power saving feature is the Selectable Core Voltage, which allows designers to choose 1.1V core voltage for high-performance applications or 0.9V core voltage for the lowest power consumption.
"Stratix III FPGAs deliver tremendous value to customers with an unmatched combination of low power, high performance and high density," said David Greenfield, senior director of product marketing for high-end FPGAs at Altera Corporation. "Combined with our Quartus II software, Stratix III FPGAs enable compelling differentiation for any high-end system designer concerned about meeting their power or performance targets."
Availability
The Stratix III EPSL150 FPGA is shipping now to customers, a month ahead of schedule. For more information about Stratix III FPGAs, please visit http://www.altera.com/stratix3.
About Altera
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at http://www.altera.com/.
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.
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