Electronic Design Verification Software includes VHDL checks.May 25, 2010 -
Ascent(TM) Lint v1.3 performs syntax and semantic Hardware Description Language (HDL) lint checks for complex SoC designs. In addition to Verilog checks, program offers Lint checking for VHDL in categories of modeling, differences between simulation and synthesis semantics, and naming/RTL coding conventions. Other categories include VHDL subset restrictions, downstream tool flow issues, network and connectivity checks, and testing.
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
Original Press release
Real Intent Inc.
3910 Freedom Circle, Suite 102A
Santa Clara, CA, 95054
USA
Real Intent Improves Its Fast, Low-Noise Electronic Design Linter; Ascent Lint Version 1.3 Extends High-Performance Linting to VHDL
SAN JOSE, California - Real Intent Inc., the innovator in automating the intelligence of formal techniques for design verification, announced today that it is shipping a new version of Ascent(TM) Lint Version 1.3. The new version adds VHDL checks to its existing Verilog checks.
Ascent Lint is the next generation lint tool in Real Intent's early functional verification family of products. It performs syntax and semantic Hardware Description Language (HDL) lint checks for today's complex SoC designs. It features an extremely fast engine and low noise report for debugging electronic designs.
What's New
Ascent Lint 1.3 adds lint checking for VHDL in the following categories:
o Ambiguous modeling
o Differences between simulation and synthesis semantics
o Naming and RTL coding conventions
o VHDL subset restrictions to enforce modeling clarity and reduce unnecessary complexity
o Operations with hidden or expensive implementation costs
o Downstream tool flow issues
o Network and connectivity checks for clocks, resets, and tristate-driven signals
o Testability
"The customer response to the initial deployments of Ascent Lint has been universally very positive," commented Pranav Ashar, Chief Technology Officer at Real Intent. "The feedback is that it is extremely easy to set up and more than an order of magnitude faster than competitive products. Ascent Lint 1.3 builds on this platform to deliver VHDL support. In addition, a key focus in this release has been to deliver an unprecedented level of usability. We are confident that with this combination of very high performance and usability, Ascent Lint 1.3 will provide compelling value in the front-end of any verification flow."
Pricing and Availability
Ascent Lint 1.3 is available now. Current customers using Ascent Implied Intent Verification (IIV) can take advantage of an upgrade package at a reduced price. For pricing information, please email info@realintent.com.
About Real Intent's Automatic Verification Software
Real Intent's automatic verification solutions include Ascent(TM), the complete solution for early functional verification; Meridian(TM), the most precise, comprehensive and innovative CDC solution in the market; and PureTime(TM), the best-in-class, comprehensive constraints validation solution with glitch-aware exception verification.
About Real Intent
Real Intent is the innovator in automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by design and verification teams worldwide. Real Intent's family of products dramatically improves the functional verification efficiency of leading edge ASICs and FPGAs devices.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web: www.realintent.com, e-mail: info@realintent.com, Twitter: RealIntent.
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