EDA Software aids in the development of SoCs.October 11, 2006 -
DesignWare® Verification IP for Open Core Protocol (OCP) interface v2.1 enables verification of OCP cores, OCP systems, and mixed OCP/AMBA systems to their external interfaces. Compliance with VMM methodology defined in Verification Methodology Manual for SystemVerilog enables integration with constrained-random, coverage-driven environments. System supports Verilog and VHDL testbenches, as well as all popular simulators.
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
Original Press release
Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA, 94043 4033
USA
Synopsys Releases Verification IP for the OCP Interface
Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups
MOUNTAIN VIEW, Calif., Sept. 13 // -- Synopsys, Inc. (NASDAQ:SNPS), a world leader in semiconductor design software, today announced that it has expanded its portfolio of DesignWare(R) Library intellectual property (IP) with the release of verification IP for the Open Core Protocol (OCP) interface. OCP is a common standard IP core interface, or socket, that facilitates "plug and play" system-on-chip (SoC) design. Synopsys has developed verification IP for the OCP interface in response to customer demand for using the DesignWare Library and VCS(R) Verification Library to verify systems and cores that utilize OCP.
The DesignWare Library and VCS Verification Library today include verification IP for AMBA(R) 2.0, AMBA 3 AXI, PCI Express(R), USB, Serial ATA, Ethernet, I2C, serial I/O and Memories. The addition of OCP 2.1 to the portfolio enables the verification of OCP cores, OCP systems, mixed OCP/AMBA systems, and OCP systems to their external interfaces. The OCP verification IP provides 100 percent coverage as defined in section 4 of the OCP 2.0/2.1 Compliance Checks document. It is compliant with the popular VMM methodology defined in the Verification Methodology Manual for SystemVerilog, enabling easy integration with constrained-random, coverage-driven environments; it also supports Verilog and VHDL testbenches. The OCP Verification IP supports all popular simulators and enables up to five times faster verification when used with the VCS comprehensive functional verification solution.
"Synopsys' DesignWare and VCS Verification IP are welcome additions to OCP's robust, thriving ecosystem," said Ian Mackintosh, president of OCP- International Partnership. "Through the support of major electronic design automation (EDA) providers like Synopsys, as well as other member companies, we are able to continue providing the latest tools and services necessary for quick, convenient adoption and implementation of the OCP standard. We look forward to working with Synopsys as the standard continues its rapid growth."
"Several of our major customers asked us to support the OCP standard with our proven DesignWare Verification IP," said Guri Stark, vice president of marketing for the Solutions Group at Synopsys. "We have worked closely with the OCP-IP organization and its member companies to bring a product to market that fully meets the needs of OCP verification."
Availability
Synopsys DesignWare Verification IP for OCP 2.1 is available on a limited basis now as part of the DesignWare Library and VCS Verification Library products. Licensees of DesignWare Library and VCS Verification Library will gain access to OCP Verification IP for no additional charge. Production release is scheduled for November, 2006.
About the VCS Verification Library
The VCS Verification Library provides the broadest portfolio of design- proven, standards-based verification IP helping designers save testbench development time and reach functional coverage goals faster. It offers advanced functionality for block and chip-level verification and is an integral part of the Synopsys Discovery(TM) Verification Platform. VCS Verification Library supports SystemVerilog, OpenVera(R), Verilog and VHDL testbenches. It supports all popular simulators and enables up to five times faster verification when used with the VCS solution. The VCS Verification Library is compliant with the popular VMM methodology, as defined in the Verification Methodology Manual for SystemVerilog, enabling easy integration with constrained-random, coverage-driven environments. The VCS Verification Library includes: AMBA 2.0, AMBA 3 AXI, OCP 2.0, PCI Express, PCI-X, PCI, USB 1.1/2.0/OTG, 10/100/1G/10G Ethernet, I2C, SATA, Serial I/O standard protocols and more than 10,000 memory models.
About Synopsys
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
NOTE: Synopsys, DesignWare, OpenVera and VCS are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys. AMBA is a registered trademark of ARM Limited. PCI Express is a registered trademark of PCI-SIG. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Web site: http://www.synopsys.com/
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