Development System helps speed complex ASIC design.March 24, 2009 -
Providing all functions needed to make complete CPU subsystem, CatsEye Development System contains CatsEye chip with 2 MIPS 24Kf cores, along with variety of interfaces such as memory controller, Flash memory controller, 2 Gb Ethernet, OCP interfaces for adding other IP to design, 3 UARTS, PCI Express device, and GPIO pins. With development system, users can do concurrent hardware and software designs and verify functionality before committing to final ASIC chip.
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
Original Press release
Kawasaki Microelectronics America, Inc.
2570 North First Street
San Jose,, CA, 95131
USA
K-micro Announces Availability of CatsEye Development Systems
New single and dual cores offer expanded options for CPU subsystem designers and greatly reduce time-to-market
SAN JOSE, Calif., March 9 / -- K-micro (Kawasaki Microelectronics), a leader in advanced ASICs, announced the availability of development systems for the MIPS32(R) 24Kf processors to speed up the hardware and software development time associated with complex ASIC designs.
The CatsEye Development system includes all the functions needed to make a complete CPU subsystem for a variety of applications ranging from internet equipment such as routers and gateways, to entertainment devices such as media players and servers. The development system enables K-micro customers to do concurrent hardware and software designs and verify functionality before committing to the final ASIC chip. This approach results in a much shorter development time because all the core functions have already been developed, tested, and proven to interoperate together. Equally important is the reduced time to production since the software was developed and debugged concurrently with the hardware. The development systems' OCP interface offers the flexibility to add specific functionality to the designs so each customer can add their own "secret sauce" to the chip and verify the operation quickly.
"Our customers will be able to develop advanced ASICs in a fraction of the time normally associated with development programs of this magnitude, saving anywhere from 6-12 months on a typical development program that normally ranges for 12-24 months," said Joel Silverman, vice president of marketing at K-micro. "Advanced tools enable our customers to rapidly add, remove or replace any of the IP with their own or a third party IP."
The development system contains a board with a CatsEye chip mounted on it, along with a variety of interfaces such as memory controller, Flash memory controller, 2 Gb Ethernets, OCP interfaces used to add other IP to the design, 3 UARTS, a PCI Express device, as well as many GPIO pins that can be used to generate additional interfaces. K-micro customers can use the CatsEye development system during the design phase of their ASICs or rent the boards if they will need them for an extended time period.
The CatsEye chip is an advanced SoC that contains a complete CPU subsystem with two MIPS 24Kf cores, two 10/100/1000 Mbit Ethernet MACs, security processor, memory controllers and host of other peripherals that are required for SoC developments. The CatsEye chip is the starting point, and customers can readily add, remove or replace any of the components to make the chip that they need.
About K-micro (Kawasaki Microelectronics)
K-micro's innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, Optical Internetworking Forum (OIF), PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Digital Living Network Alliance (DLNA), Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), Multimedia over Coax Alliance (MoCA), and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit http://www.k-micro.us/
MIPS, MIPS32, 24Kc, 24Kf, 24KEc, 24KEf, 34Kc, 34Kf, 74Kc, 74Kf and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners.
Web Site: http://www.k-micro.us/
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