Controller IP Core supports up to 240 GBps.
June 20, 2012 -
Integrating benefits of HMC technology into next-generation systems, Hybrid Memory Cube Controller IP Core targets high-performance computing, networking, and test/measurement applications. As fully synchronous, soft-core implementation suitable for ASICs and FPGAs, core supports up to 4 HMC links managed by single controller, along with error detection and automatic retry. Each link consists of 16 lanes of 10, 12.5, or 15 Gbps.
|Original Press release |
490 N. McCarthy Blvd Suite 220
Milpitas, CA, 95035
Open-Silicon Announces Industry's First Hybrid Memory Cube Controller IP
Enabling Next-Generation Memory System Design for High-Performance Computing, Networking and Test & Measurement Applications
MILPITAS, Calif., -- Open-Silicon, Inc., a leading semiconductor design and manufacturing company, announced today the industry's first Hybrid Memory Cube (HMC) controller IP core - the industry's highest-performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems. Targeting high-performance computing, networking and test & measurement applications, the HMC controller IP core builds upon Open-Silicon's deep expertise in high-bandwidth serial protocols derived from Open-Silicon's industry-leading Interlaken controller IP core.
The HMC technology represents an entirely new category of high-performance memory, delivering revolutionary performance and low power in a dramatically reduced footprint. To benefit from this technology, next generation system developers need a high quality, customizable, and easy to integrate HMC controller IP to quickly get their products to market. Open-Silicon's unique experience in complex ASIC development, combined with deep serial protocol IP expertise from developing six generations of Interlaken controllers, makes it a natural fit to offer this solution. As a result, Open-Silicon joined the Hybrid Memory Cube Consortium (HMCC) as a developer member and has been using that collective experience to help craft the advanced specification requirements for the HMC interface.
"The mission of the Hybrid Memory Cube Consortium is to facilitate HMC integration into a wide variety of systems, platforms and applications," said Scott Graham, general manager of Hybrid Memory Cube for Micron Technology, co-founder of the HMCC. "We are excited by Open-Silicon's efforts to enable the adoption of HMC technology."
The Open-Silicon IP offers a seamless way to interface with HMC. Supporting up to 240GBps, the high-performance HMC controller IP also offers ultra-low latency and a flexible user interface. As a fully synchronous, soft-core implementation suitable for ASICs and FPGAs, along with robust error detection and automatic retry, the core supports up to four HMC links managed by a single controller. Each link consists of 16 lanes of 10, 12.5 or 15 Gbps.
"We believe that 3D IC technology is the future of semiconductors. When we joined HMCC as one of the first developer members, we did this with the intent of enabling, and bringing to market, this revolutionary technology," said Steve Erickson, VP of IP and Platforms, Open-Silicon. "The HMC controller IP is highly configurable, and will enable our customers to enjoy greater differentiation in the market."
About Open-Silicon, Inc.
Open-Silicon® is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, IP, system software, and high-quality semiconductor manufacturing services with one of the world's broadest partner ecosystems for IC development. For more information, visit Open-Silicon's website at www.open-silicon.com or call 408-240-5700.
CONTACT: Hillary Cain, Marketing Manager, +1-415-350-4860, Hillary.firstname.lastname@example.org
Web Site: http://www.open-silicon.com/