Adaptive Clock Translators suit wired communication applications.October 27, 2011 -
Integrating low-phase-noise, frequency-agile VCO and loop filter along with dynamic adaptive clock support, dual-input Model AD9557 and quad-input Model AD9558 translate any standard input frequency to any standard output frequency from 2 kHz to 1.25 GHz with sub-400 fs RMS total jitter on 12 kHz to 20 MHz. Adaptive clocking allows DPLL divider ratios to be changed while DPLL is locked. Fully programmable, ICs enable line card designers to use same component in many board designs.
Original Press release
Analog Devices Inc
1 Technology Way, P.O. Box 9106
Norwood, MA, 02062
USA
Multiservice Line Card Adaptive Clock Translators Support Wide Range of Wired Communications Applications
NORWOOD, Mass.-- Analog Devices, Inc. (ADI) introduced today two fully programmable jitter attenuating clock translators ICs (integrated circuits) that perform frequency translations for a wide range of wired communications applications -- including Synchronous Ethernet and SONET/SDH optical networks -- that require low jitter, fast time to market and cost effectiveness,. The AD9557 dual-input multiservice line card adaptive clock translator and the AD9558 quad-input multiservice line card adaptive clock translator translate any standard input frequency to any standard output frequency from 2 kHz to 1.25 GHz with sub-400-fs RMS total jitter on 12 kHz to 20 MHz.
The new clock translators outperform traditional PLL (phase locked loop) designs that require the addition of expensive VCXOs (voltage-controlled crystal oscillators).
o Download data sheet and order samples: www.analog.com/AD9557 or www.analog.com/AD9558
o Webinar: Network Clocks: How to Achieve Maximum System Up Time http://www.analog.com/network_clock
The built-in programmability of the AD9557 and AD9558 clock translators allow network line card designers to use the same component in many different board designs limiting the number of components needed and reducing overall system cost. This includes synchronization for a wide variety of high-performance applications, including data communications, next-generation wired networking applications, telecommunications, test and measurement, high speed data acquisition and wireless base station controllers.
The AD9557 and AD9558 clock translators integrate an on-chip, low-phase-noise, frequency-agile VCO (voltage-controlled oscillator) and loop filter along with dynamic adaptive clock support. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency value at the output to be dynamically adjusted by up to +/- 100ppm from the nominal output frequency without manually breaking the loop and reprogramming the part with a sub 0.1 ppb step in frequency resolution. This adaptive clock function is used for applications such as SDH to OTN mapping/demapping and asynchronous mapping/demapping. The adaptive clock translators' programmable DPLL supports loop bandwidth from 0.1 Hz to 5 kHz and features three separate programming modes for ease of use and flexibility. The two devices are pin- or soft-pin pre-configured to support popular SONET/SDH, Ethernet, Synchronous Ethernet and Fiber Channel frequencies, while SPI (serial port interface) and I2C ports are available to program customized input-to-output frequency translation.
At 6 mm x 6 mm and 9 mm x 9 mm in size, respectively, the AD9557 and AD9558 clock translators provide compact, frequency agile, cost effective clocks for line card designers. The AD9557 features two reference inputs (single-ended or differential) and two pairs of clock outputs. Each output pair is configurable as a single differential LVDS/HSTL output or as two single-ended CMOS outputs. The AD9558 offers the same features but with four reference inputs and six pairs of clock outputs.
Key Features of the AD9557 and AD9558 Adaptive Clock Translators
o Supports GR-1244 Stratum 3 stability in holdover mode.
o Provides smooth reference switchover with virtually no disturbance on output phase.
o Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 Systems.
o Supports ITU-T G.8262 Synchronous Ethernet slave clocks.
o Supports ITU-T G.823, G.824, G.825, and G.8261.
Availability, Pricing and Complementary Parts
Product Availability Temperature Range Price Each Per 1,000 Packaging
AD9557 Full Volume
Production Now -40°C to 85°C $15 40-lead LFCSP
6 mm x 6 mm
AD9558 Full Volume
Production Now -40°C to 85°C $16.25 64-lead LFCSP
9 mm x 9 mm
AD9577 Sampling Now -40°C to 85°C $7.23 40-lead LFCSP
6 mm x 6 mm
The asynchronous AD9577 clock generator with dual PLLs complements the AD9557 and AD9558 clock translators by providing key elements of the clock tree for various applications. It is a cost- effective asynchronous clock solution for oscillator replacements and generates local clocks for processors, FPGAs, or PHYs in SONET/SDH, Synchronous Ethernet applications, Ethernet enterprise switches, core/edge router fabric cards and line cards as well as in packet transmission networks (PTN) and fiber channel applications.
About Analog Devices
Innovation, performance, and excellence are the cultural pillars on which Analog Devices has built one of the longest standing, highest growth companies within the technology sector. Acknowledged industry-wide as the world leader in data-conversion and signal-conditioning technologies, Analog Devices serves over 60,000 customers, representing virtually all types of electronic equipment. Analog Devices is headquartered in Norwood, Massachusetts, with design and manufacturing facilities throughout the world. Analog Devices' common stock is listed on the New York Stock Exchange under the ticker "ADI" and is included in the S&P 500 Index. http://www.analog.com
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Contacts
Analog Devices Inc.
Bob Olson, 781-937-1666
bob.olson@analog.com
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