Quantcast
 
Search for: Search what?
Nov 22, 2009  
 Sections
Latest New Product News
Industry Market Trends
Green & Clean News
Association & Government News
Adhesives and Sealants
Agricultural and Farming Products
Architectural and Civil Engineering Products
Automatic ID
Chemical Processing and Waste Management
Cleaning Products and Equipment
Communication Systems and Equipment
Computer Hardware and Peripherals
Construction Equipment and Supplies
Controls and Controllers
Display and Presentation Equipment
Electrical Equipment and Systems
Electronic Components and Devices
Explosives, Armaments and Weaponry
Fasteners and Hardware
Fluid and Gas Flow Equipment
Food Processing and Preparation
Health, Medical and Dental Supplies and Equipment
HVAC
Labels, Tags, Signage and Equipment
Laboratory and Research Supplies and Equipment
Lubricants
Machinery and Machining Tools
Material Handling and Storage
Materials and Material Processing
Mechanical Components and Assemblies
Mechanical Power Transmission
Mining, Oil Drilling & Refining
Mounting and Attaching Products
Non-Industrial Products
Optics and Photonics
Packaging Products & Equipment
Paints and Coatings
Plant Furnishings and Accessories
Portable Tools
Printing and Duplicating Equipment
Retail and Sales Equipment
Robotics
Safety and Security Equipment
Sensors, Monitors and Transducers
Services
Software
Test and Measuring Instruments
Textile Industry Products
Thermal and Heating Equipment
Timers and Clocks
Transportation Industry Products
Vision Systems
Waste Handling Equipment
Welding Equipment and Supplies
 Press Releases
Products in the News
Company News
Mergers & Acquisitions
People in the News
Literature & Websites
 Resources
News Delivery Options
Browse Categories
Browse Companies
Mobile Edition
PR Resources
Licensing
Advertising
How to Write an effective Press Release
Trade Associations
Small Business Support
MEP
Advertisement

PHY IP supports 28 nm processes in 1.8 V architecture.


November 5, 2009 - Designed for smartphones, mobile Internet devices, and netbooks, DesignWare® USB 2.0 picoPHY IP supports Battery Charging v1.1 specification, which allows mobile devices to draw up to 1.8 A of current when connected to wall charger. By supporting USB On-the-Go v2.0 specification, DesignWare USB 2.0 picoPHY incorporates Attached Detection Protocol feature, which optimizes power efficiency of portable devices that communicate directly to USB peripherals without need for PC host.

 See related product stories
FPGA Design Software supports high-speed DDR interfaces.
Channel Simulator Software includes bit-error-rate detection.
Processor Cores offer 32-bit performance and 16-bit code.
Dataplane Core targets DSP applications.
Simulation Library helps algorithm, hardware developers.
 See more product news in:
Mechanical Components and Assemblies
Software
 Tools for you
del.icio.us DIGG  
Facebook Reddit
StumbleUpon Twitter
Print This Page E-Mail Story
Watch_Company  Save Story
Contact company View Company Profile
Company web site 
More news from this company

Advertisement
More Tools and information
Search for suppliers of
Electronic Design Automation (EDA) Software
Central Processing Unit (CPU), Intellectual Property (IP), Microprocessor & Processor Cores
Join the forum discussion at:
 Engineers Lounge
 Tools of the Trade
 Newsletters
Your Gateway to a Fast Changing World
Product News Alerts
Receive similar stories and other customized news to keep you in the know on the products shaping industry.
Subscribe Free Today
Subscribe   View Sample

Industry Market Trends
Has Got It
  • Latest developments
  • Trends
  • Best practices
  • Opinions & Commentary
Get Ahead. Get IMT.
Subscribe Free Today
Subscribe   View Sample
 See more related product stories:
EDA Software suits pin-limited semiconductor testing.
PCB Design Prototyping Software accelerates board development.
Dataplane Processor Core offers deeply embedded control.
Design and Verification Software offers S-Parameter support.
Transmit/Receive Controller supports HDMI.
Electrical Engineering Software aids wiring design and layout.
PCB Design Software combines board-level and hardware design.
PCB Design Software focuses on ease of use and quality.
Electronic Design Automation Software facilitates, accelerates ASIC/FPGA development.
PHY and Controller IP supports 1,866 and 2,133 Mbps data rates.
IC Design Software provides custom parasitic extraction solution.
Development Board enables prototyping of electronic designs.
Functional Verificaton Software ensures X-robust designs.
IP Software facilitates FPGA design.
DSP IP Core is suited for LTE and 4G SOC designs.
Software validates electronic designs automatically.
DSP Core targets wireless handsets and base stations.
Desing Platform Kits accelerate development of SoCs.
IP Core aids wireless basestation, remote radio head design.
MMIC Design Kit supports TQPED E/D pHEMT process.


Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes


Connectivity IP Leader Continues to Innovate with the DesignWare USB 2.0 picoPHY - The First PHY IP to Support USB 2.0 Battery Charging v1.1 and OTG 2.0 Specifications

MOUNTAIN VIEW, Calif., Oct. 29 /-- Synopsys, Inc. (NASDAQ:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of the new DesignWare® USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in more than 50 different process technologies ranging from 180-nanometer (nm) to 32-nm. Targeted at mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices and netbooks, the DesignWare USB 2.0 picoPHY supports advanced 28-nm processes in a 1.8V architecture, is 30 percent smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption.

The DesignWare USB 2.0 picoPHY IP is the first PHY IP to support the new Battery Charging version 1.1 and USB On-the-Go (OTG) version 2.0 specifications from the USB Implementer's Forum (USB-IF). The Battery Charging v 1.1 specification allows mobile devices to draw up to 1.8 A of current when connected to a wall charger. The Battery Charging specification enables portable devices to distinguish among various power sources, such as a wall charger, standard host port and USB charging port, and selects the most efficient method to charge the device. By supporting the USB OTG version 2.0 specification, the DesignWare USB 2.0 picoPHY incorporates the new Attached Detection Protocol (ADP) feature, which improves the power efficiency of portable devices that communicate directly to USB peripherals without the need for a PC Host. In addition the DesignWare USB 2.0 picoPHY supports advanced power management features, such as power supply gating and support for ultra-low standby current to help designers lower the leakage power of mobile system-on-chips (SoCs) while maintaining the integrity of the USB 2.0 connection.

"Delivery of USB IP solutions from providers like Synopsys helps system designers benefit from the latest functionality offered by USB technology," said Jeff Ravencraft, president and chairman of the USB Implementers Forum. "With the prevalence of USB on mobile devices, IP solutions like Synopsys' new DesignWare USB 2.0 picoPHY IP will enable designers to quickly incorporate this technology into their SoCs designs and bring new USB-enabled products to the market quickly."

"For nearly a decade, designers have successfully incorporated Synopsys' high-quality DesignWare USB 2.0 PHY IP into their SoCs which they have shipped in hundreds of millions of units," said John Koeter, vice president of marketing of the Solutions Group at Synopsys. "The addition of the new DesignWare USB 2.0 picoPHY IP to this already widely adopted product line provides designers with a competitive edge through our continued innovation and support for the latest processes and specifications."

Availability

The DesignWare USB 2.0 picoPHY IP is expected to be available to early adopters starting in Q4 2009 for 28-nm processes, with a roadmap for 40- and 32-nm. For more information please visit: http://www.synopsys.com/usb.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven interface and analog IP solutions for system-on-chip designs. Synopsys' broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, HDMI, MIPI and Ethernet. The analog IP family includes Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transaction-level models to build virtual platforms for rapid, pre-silicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware

Follow us on Twitter at http://twitter.com/designware_ip.

About Synopsys

Synopsys, Inc. (NASDAQ:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys and DesignWare are registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Web Site: http://www.synopsys.com/




Contacts:

Public Relations:
MCA
Karen Do
USA
Phone: 650-968-8900 ext 108
Send email  E-mail this person

Company Information:
Name: Synopsys, Inc.
Address: 700 E. Middlefield Rd.
City: Mountain View
State: CA
ZIP: 94043 4033
Country: USA
Phone: 650-584-5000
http://www.synopsys.com/


More New Product News from this company:
EDA Software suits pin-limited semiconductor testing.
Transmit/Receive Controller supports HDMI.
Electronic Design Automation Software facilitates, accelerates ASIC/FPGA development.
PHY and Controller IP supports 1,866 and 2,133 Mbps data rates.
IC Design Software provides custom parasitic extraction solution.
EDA Software speeds throughput for electronic design.
EDA Software provides look-ahead constraint analysis.
IP Components slash power in datapath circuits.
Analog Simulation Software offers schematic driven layout.

Other News from this company:
SMIC and Synopsys Announce the Availability of Reference Flow 4.0
Synopsys CFO Brian Beattie to Speak at Citi Small and Mid-Cap Conference
Synopsys CEO Aart de Geus to Speak at the 2008 Morgan Stanley Technology Conference
Synopsys and SMIC Deliver Enhanced 90-Nanometer Reference Flow to Reduce IC Design and Test Costs
Synopsys Unveils Proteus Pipeline Technology, Delivering a New Level of Performance
Synopsys Experts on the Road IP Seminar and Keynote Luncheon with Jeff Ravencraft, President of the USB-IF
Radiospire Standardizes on Synopsys VCS and VMM Methodology for Next- Generation AirHook Chipset Designs
Synopsys CFO Brian Beattie to Speak at D.A. Davidson Electronic Systems Design Conference
Synopsys and Acceleware Deliver Hardware Accelerated Solution for Design of Optoelectronic Devices
Magma, Mentor Graphics and Synopsys Deliver Unified Power Format-Based Products
Synopsys IC Compiler Successfully Employed by Matsushita for First 45-nm SoC Design Tapeout
Synopsys CEO Aart de Geus to Speak at the Needham Growth Conference January 8, 2008
Synopsys and UMC Deliver 65-Nanometer Reference Flow
Synopsys Acquires Sandwork Design
Global Unichip Adopts Synopsys Test Solution to Achieve Higher SoC Test Quality
Synopsys Recognizes Engineers' Technical Excellence with Best Paper Awards at SNUG Boston Conference
eRide Converts to Synopsys Design Compiler Ultra for Next-Generation GPS Chips
Synopsys and SMIC Jointly Address China Mobile TV Market with Low Power Design Solution
Synopsys Senior Vice President to Speak at the 2007 Citi Global Technology Conference
Synopsys Completes Acquisition of MOSAID Semiconductor IP Assets



Click here for copyright permissions!
Copyright 2009 Thomas Publishing Company


 

Post a comment about this story

Name:
E-mail:
(your e-mail address will not be posted)
Comment title:
Comment:
 

Category Advertisements
Home  |  My ThomasNet News  |  Industry Market Trends  |  Submit Release  |  Advertise  |  Contact News  |  About Us
Brought to you by Thomasnet.com        Browse ThomasNet Directory

Copyright © 2009 Thomas Publishing Company
Terms of Use - Privacy Policy