OpenCL Software Development Kit fosters FPGA exploitation.

Altera Corporation    San Jose, CA 95134
May 14, 2013 SDK for OpenCL and supported third-party production boards enables software programmers to access high-performance capabilities of programmable logic devices. Designed to foster increased system performance in highly data-parallel computing applications featured in financial, military, broadcast, and medical markets (among others), SDK lets programmers take OpenCL code and exploit massively parallel architecture of FPGA.

CAE Software accelerates FPGA design.

Altera Corporation    San Jose, CA 95134
May 14, 2013 Intended for users targeting 28 nm FPGAs and SoCs, including Stratix® V FPGAs, Quartus® II v13.0 helps enhance FPGA and SoC performance and designer productivity. Solution offers high-level C-based, system-/IP-based, and model-based design flows as well as DSP Builder design tool. While SDK for OpenCL makes massively-parallel FPGA-based accelerators available to software programmers without FPGA experience, Qsys system integration tool provides support for ARM®-based Cyclone® V SoCs.

SoC Development Kit includes FPGA-adaptive debugging software.

Altera Corporation    San Jose, CA 95134
May 03, 2013 With Cyclone® V SoC Development Kit, hardware and software developers can accelerate embedded systems design development. Kit includes ARM® Development Studio 5 Altera® Edition Toolkit, an FPGA-adaptive debugging software that enables designers to view processor and FPGA portions of device simultaneously. Kit also features Cyclone V SX SoC with 800 MHz dual-core ARM Cortex™-A9 processor, 110K LEs of logic density, 3.125 Gbps transceivers, PCIe® rootport and endpoint support, and DDR3 memory.

Low-Power, 5 Gbps FPGA complies with PCIe 2.0 specifications.

Altera Corporation    San Jose, CA 95134
Mar 25, 2013 Integrating transceivers with data rates up to 5 Gbps, 28 nm Cyclone® V GT FPGA features 2 hardened PCIe IP blocks, embedded, that enable developers to increase system performance and system functionality. PCIe 2.0-compliant hard IP blocks, which consists of PHY/MAC, data link, and transaction layers, can be configured to function as end point or root port and support up to x4 lanes. Multifunction support feature allows up to 8 PCIe end points to be combined into single end point.

FPGA-Based HSR/PRP Reference Design targets smart grid equipment.

Altera Corporation    San Jose, CA 95134
Mar 04, 2013 High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design, facilitating development and implementation of mission-critical communications systems in smart grid substations, includes Flexibilis Redundant Switch (FRS) IP implemented on Altera® Cyclone®-class FPGA or Cyclone V SoC. Flexibilis HSR/PRP IP consists of triple-speed 10/100/1000 Mbps Ethernet Layer 2 switch, scalable from 3–8 ports, that complies with IEC 62439-3 standard.

SoC Devices offer 32-bit ECC support.

Altera Corporation    San Jose, CA 95134
Dec 14, 2012 Combining dual-core ARM® Cortex™-A9 processor with FPGA logic, 28 nm Cyclone® V SoCs enable developers to create custom SoC variants optimized for system power, board space, and performance. Error Correction Code functionality, built into SoC's external DRAM interface, helps ensure data integrity throughout embedded system. Other features include high-bandwidth memory controller with built-in memory protection, flexible boot capability, and integrated PCIe® across all SoC devices.

Motor Control Design System offers scalable performance.

Altera Corporation    San Jose, CA 95134
Nov 26, 2012 In addition to customizable, single and multiaxis drive-on-a-chip reference designs, FPGA-based Motor Control Development Framework includes motor control hardware development boards, coupled with system and software design methodology, to support requirements of next-generation drive systems. System allows designers to use high-level software algorithms for system management and higher-level control functions integrated with accelerated low-latency control loops implemented in FPGA.

Safety Data Software accelerates design certification process.

Altera Corporation    San Jose, CA 95134
Nov 20, 2012 Leveraging diverse device and software support, 2012 functional safety data package helps those using Cyclone® IV FPGAs reduce risks and adhere to safety regulations when developing safety-critical designs for automotive, industrial, medical, and defense applications. Package provides safety design flow, IP, and development tools necessary for designs that must comply up to SIL3. Included safety IP cores ensure system integrity in accordance with IEC 61508.

Software Development Tools helps build FPGA-based applications.

Altera Corporation    San Jose, CA 95134
Nov 16, 2012 Combining massively parallel architecture of FPGA with OpenCL (Open Computing Language)  parallel programming model, SDK for OpenCL™ helps system developers and programmers familiar with C develop FPGA-based applications in high-level language. Solution enables FPGAs to work in concert with host processor to accelerate parallel computation with minimal power consumption. Unified, high-level design flow for hardware and software development automates tasks required in typical HDL flows.

Midrange FPGA suits broadcast and communications applications.

Altera Corporation    San Jose, CA 95134
Oct 12, 2012 Featuring 36 backplane-capable transceivers that operate at up to 12.5 Gbps, 28 nm Arria® V GZ FPGA is suited for remote radio units, LTE wireless communication equipment, in-studio mixers, and 10 G/40 G line cards. Device includes hardened PCI Express® Gen3 protocol stacks, soft IP-based memory controllers, and 4 separate DDR3 DIMM interfaces at 72 bits wide operating at 1,600 Mbps. Anti-tamper features include AES and both on-board and off-board key programming.