Software is used for system level design and verifications.

Mentor Graphics Corp.    San Jose, CA 95131
Jun 25, 2008 With full support for IP-XACT 1.4 IP databook specification, Platform Express is tool that allows IP to be automatically integrated into designs using range of IP-XACT enabled tools. It has mixed-level RTL and ESL design capabilities to help deploy system level modeling and verification methodologies, bridging the gap between ESL and RTL centric design/validation flows. Software also supports TGI generator format of IP-XACT 1.4 specification.

Debugging Software targets processor driven tests.

Mentor Graphics Corp.    San Jose, CA 95131
Jun 25, 2008 Able to validate ASICs containing 1 or more embedded processors, Questa® Codelink(TM) is source-level debugger for RTL processor models supplied by ARM and MIPS. It helps organize and view representations of data associated with multi-core source-level debug. Software can log batch runs and debug interactively post-simulation, eliminating need to rerun long simulations in order to debug them. Product replays 15 hr simulation in 3 sec, and supports stepping backwards through source or assembly.

RF Design Kit covers mixed-mode and logic sub-processes.

Mentor Graphics Corp.    San Jose, CA 95131
Jan 14, 2008 RF process design kit combines 65 nm mixed-signal and RF process technology with ICStudio(TM) custom IC design platform. It features devices such as High-Q inductors, MiM and metal fringe capacitors, Deep N-Well isolation, and multiple Vt devices. Design kit also comes with packaged RF flow tutorial, which encapsulates flow between analog design tools, foundry process information, and design methodology.

IP Core facilitates developmet of SATA storage solutions.

Mentor Graphics Corp.    San Jose, CA 95131
Jan 14, 2008 MSATA PHY S130A IP core is designed for Semiconductor Manufacturing International's 130 nm Generic process. With integrated Serial ATA controllers, PHY IP core targets both host and device applications running at either 1.5 or 3.0 Gbps. It features analog circuitry residing in I/O ring, less than 3 mm² footprint, and low power optimization with less than 75 mW per lane including termination power.