Latest New Product News from Cadence Design Systems, Inc.
Rapid Prototyping Platform supports low-power verification.Cadence Design Systems, Inc. San Jose, CA 95134
Jul 22, 2014 System Development Suite includes CadenceŽ Protium™ rapid FPGA prototyping platform for software development as well as IEEE 1801 low power standard verification and debug support in Cadence PalladiumŽ XP II verification computing platform. These features enable system and semiconductor companies in mobile, consumer, networking and storage segments to address such design challenges as early software bring-up and reduced power consumption.
EDA Software offers tool for RC extraction.Cadence Design Systems, Inc. San Jose, CA 95134
Jul 21, 2014 With massively parallel architecture, CadenceŽ Quantus™ QRC Extraction Solution accelerates design signoff and sets standard for performance by accelerating runtime for single and multi-corner extraction. Tool is TSMC certified for 16 nm FinFET designs, supports both SoC and custom/analog designs, and includes Quantus FS foundry-certified integrated random-walk field solver. Automated incremental extraction capability minimizes design closure turnaround time.
EDA Software cuts die-package interconnect planning time.Cadence Design Systems, Inc. San Jose, CA 95134
May 30, 2014 Used early in design cycle, CadenceŽ OrbitIO™ provides rapid planning of interfaces across multiple fabrics. As part of overall co-design solution, Cadence OrbitIO integrates with Cadence SiP Layout and Cadence EncounterŽ digital implementation platform, allowing design teams to clearly communicate design intent throughout flow. Software can enable fabless semiconductor or systems companies to evaluate package route feasibility, and communicate route plan to package design resources.
DDR4 PHY IP targets microserver market.Cadence Design Systems, Inc. San Jose, CA 95134
May 28, 2014 Built on 16 nm FinFET process, CadenceŽ DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps.
EDA Software accelerates timing closure of PCB interfaces.Cadence Design Systems, Inc. San Jose, CA 95134
Mar 13, 2014 Available within CadenceŽ Allegro PCB Designer, AllegroŽ TimingVision™ uses embedded timing engine to analyze entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on canvas. When combined with Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.
Imaging/Video Dataplane Processor handles complex functions.Cadence Design Systems, Inc. San Jose, CA 95134
Feb 27, 2014 TensilicaŽ Imaging and Video Processor-Enhanced Performance (IVP-EP) core is available as configurable core and complete, pre-built subsystem. Integrating DMA transfer engine with up to 10 GBps throughput and local memory throughput of 1,024 bits per cycle, 4-way VLIW architecture delivers parallelism intermixed with code-compact instructions, with 32-way vector SIMD dataset. Imaging-specific operations accelerate 8-, 16-, and 32-bit pixel data types and video operation patterns.
Baseband DSP IP Cores are optimized for low-power applications.Cadence Design Systems, Inc. San Jose, CA 95134
Feb 26, 2014 Respectively, TensilicaŽ ConnX BBE32EP and BBE64EP are 32- and 64-MAC baseband DSP IP cores optimized for complex number processing at low power. Products excel at processing algorithms for LTE, LTE-Advanced, 802.11ac, HDTV demodulation, 3G/HSPA+, and WiFi (including MIMO processing). Supporting power consumption levels that reduce need for hardware accelerators, cores suit such applications as smartphones and tablets, HDTVs, STBs, and automotive communications infrastructure systems.
EDA Software accelerates SoC verification closure.Cadence Design Systems, Inc. San Jose, CA 95134
Jan 20, 2014 For IP block-to-chip verification, Incisive v13.2 includes Trident engine that optimizes formal analysis, and constraint engine that speeds Universal Verification Methodology and SystemVerilog testbench simulation. IEEE 1647 e unit testing without simulation cuts debug time for testbench code. For SoC verification, program supports x-propagation to speed SoC reset and low-power simulations. Support for SystemVerilog IEEE 1800-2012 real number modeling enables faster mixed-signal simulation.
Software facilitates design of nanometer wireless chips.Cadence Design Systems, Inc. San Jose, CA 95134
Dec 07, 2007 VirtuosoŽ Passive Component Designer delivers complete flow for design, analysis, and modeling of inductors, transformers, and transmission lines. Optimized for 90 and 65 nm process nodes, solution supports advanced design rules and CMP constraints such as dummy metal fills and slotting. Modeling capability converts S-parameter files into physical lumped element models ready for RF analysis, and built-in 3D full wave solver verifies generated devices.
IC Design Software uses hierarchical design capabilities.Cadence Design Systems, Inc. San Jose, CA 95134
Mar 19, 2002 Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. Cadence SoC Encounter front-to-back hierarchical IC implementation provides solutions for large-scale system-on-a-chip (SoC) design with 30-million gate synthesis and place-and-route capability. SoC Encounter partitions chips into smaller blocks to be designed separately and later reassembled.
Click below for more Product News from Cadence Design Systems, Inc.
Other Company News From Cadence Design Systems, Inc.
Jun 23, 2014
Cadence and QNX Announce New Tensilica HiFi Audio/Voice DSP Application for In-Car Active Noise Control
May 27, 2014
Cadence Offers Production Proven USB 3.0 Host Controller IP
May 27, 2014
Cadence to Showcase Comprehensive PCI Express IP and Verification Solutions at PCI-SIG 2014
May 20, 2014
Cadence Extends Spectre XPS to Support Mixed-Signal Designs
May 15, 2014
Cadence Announces Immediate Availability of Industry's First Verification IP for PCI Express 4.0 Technology
Apr 15, 2014
Cadence Digital and Custom/Analog Tools Achieve TSMC V1.0 DRM Certification for 16nm FinFET Process
Mar 12, 2014
Cadence and GLOBALFOUNDRIES Announce First Test Chip Featuring ARM Cortex-A12 Processor in 28nm-SLP Process
Feb 25, 2014
Global Navigation Satellite Receiver From Galileo Satellite Navigation Now Available on Cadence Tensilica ConnX DSP IP Cores
Feb 19, 2014
Cadence and Sensory Reduce Voice Activation Power Dissipation in Mobile Devices to Less than 17 MicroWatts
Feb 12, 2014
Cadence Showcases System Development Solutions for Advanced Driver Assistance Systems at Embedded World 2014
Jan 29, 2014
Cadence DDR4 PHY IP Achieves 2667 Mbps Performance - Fastest in the Industry
Jan 15, 2014
DesignCon 2014: Get a Sneak Peak of Sigrity 16.63 at Cadence Booth #507
Jan 14, 2014
Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development
Dec 03, 2007
UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65nm Designs
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