IC Engineering Software accelerates design process.

Synopsys, Inc.    Mountain View, CA 94043 4033
May 14, 2013 In addition to providing foundation of design closure technologies, IC Compiler™ 2013.03 features optimizations that enable high-speed design; efficient implementation of final-stage engineering change orders (ECO); and fully color-ready, tapeout-proven support for emerging FinFET-based silicon processes. To enable high-speed clock design, clock estimation is performed during placement to drive physical- and timing-aware clock gating concurrently with clock and data optimization.

EDA Software addresses memory test and repair at 20 nm and below.

Synopsys, Inc.    Mountain View, CA 94043 4033
Nov 20, 2012 Automated pre- and post-silicon memory test, debug, diagnostic, and repair solution, DesignWare® STAR Memory System®, helps designers improve QoR, reduce design time, lower test expense, and optimize manufacturing yield. Solution targets 20 nm- and FinFET-based designs, and architecture enables hierarchical implementation and validation of SoC designs containing thousands of embedded memories. Functionality also addresses test/repair for memory defects seen in 20 nm processes and below.

Optical Engineering/Design Software reduces manufacturing costs.

Synopsys, Inc.    Mountain View, CA 94043 4033
Oct 15, 2012 CODE V® v10.5 supports optimization, analysis, and tolerancing of image-forming optical systems and free-space photonic devices. Direct optimization method can reduce sensitivity of optical systems to manufacturing tolerances, improve as-built performance, and minimize production expenditure. Irregularity model for Monte Carlo-based tolerancing, included, provides flexibility and robustness for modeling optical surface shape irregularities and their impact on as-built system performance.

IC Verification Software supports complex 20 nm designs.

Synopsys, Inc.    Mountain View, CA 94043 4033
Sep 10, 2012 Offering physical verification platform for advanced process nodes, IC Validator 2012.06 can perform decomposition checks during design and can drive automatic fixing of violations with IC Compiler via In-Design technology. Program can also perform final signoff quality check alongside final design rule check. Pattern-matching technology augments DRC with intuitive 2D multi-shape pattern analysis for detection of manufacturing hotspots.

EDA Software accelerates virtual prototype creation.

Synopsys, Inc.    Mountain View, CA 94043 4033
Jul 30, 2012 With model authoring feature and IP specification import function, Virtualizer(TM) enables engineers to rapidly develop system-level models and assemble them into virtual prototypes. Graphical simulation profiler can be used to find and address simulation bottlenecks. Out-of-the-box support for APIs in software debuggers such as Lauterbach TRACE32 System and ARM Development Studio 5 enables teams to use VDKs to create integrated environment for multicore software debug.

IC Compiler Software supports giga-performance design.

Synopsys, Inc.    Mountain View, CA 94043 4033
Jul 25, 2012 Part of Galaxy(TM) Implementation Platform, IC Compiler(TM) v2012.06 contains several technologies geared towards boosting design frequency. Multisource clock tree synthesis leverages automated clock tree and mesh techniques to optimize variation tolerance, while algorithms leverage advanced process effects to optimize timing, minimize buffer count, and create robust circuits for reduced variability. For designs with highly fragmented floorplans, program can improve timing and routability.

PCI Express Controller IP supports low power sub-states.

Synopsys, Inc.    Mountain View, CA 94043 4033
Jul 17, 2012 With DesignWare® Controller IP for PCI Express 1.0, 2.0, and 3.0, designers can minimize power consumption in cameras, card readers, networking, and wireless applications. L1.1 (snooze) and L1.2 (off) sub-states reduce PCI Express system's link idle power consumption from 15-20 mW per lane to 10 µW per lane, or by approximately 99%, by repurposing signals between PHY and controller so that they turn off high-speed circuits in PHY when not in use.

EDA Software facilitates lighting systems design.

Synopsys, Inc.    Mountain View, CA 94043 4033
Jun 26, 2012 Equipped with Street Lighting Utility, LightTools® v7.3 guides users through process of evaluating, designing, and optimizing luminance and illuminance patterns on roadways to meet industry-standard specifications. Color Quality Scale and Gamut Area Index help measure color quality of LED sources, while phosphor modeling processes help streamline phosphor material manufacturing for solid-state lighting applications. With Optical Property Manager, users can manage design data.

SoC Prototyping Systems enhance debug visibility.

Synopsys, Inc.    Mountain View, CA 94043 4033
May 04, 2012 HAPS® FPGA-based prototyping systems offer HAPS Deep Trace Debug, which enhances capacity and fault isolation capabilities while freeing up on-chip FPGA memory required for validating complex SoC designs. By pairing the Synopsys® Identify® Intelligent Integrated Circuit Emulator with HAPS Deep Trace Debug SRAM daughter board, HAPS Deep Trace Debug allows various signal probes with complex triggers to be recorded and provides memory sufficient to store state history as system executes.

EDA Software accelerates FPGA synthesis and prototyping.

Synopsys, Inc.    Mountain View, CA 94043 4033
Apr 11, 2012 Synplify Pro® and Synplify® Premier are 2012.03 products that include synthesis algorithms that accelerate runtime. Additionally, Synplify Premier offers continue-on-error feature that lets FPGA designers' generate report and fix all errors resulting from missing or incorrect design definitions at end of hardware description language (HDL) compilation step. Functionality also automates process of building high reliability and fault tolerance aspects into FPGA design.