Controller IP Core supports up to 240 GBps.

Open-Silicon, Inc.    Milpitas, CA 95035
Jun 20, 2012 Integrating benefits of HMC technology into next-generation systems, Hybrid Memory Cube Controller IP Core targets high-performance computing, networking, and test/measurement applications. As fully synchronous, soft-core implementation suitable for ASICs and FPGAs, core supports up to 4 HMC links managed by single controller, along with error detection and automatic retry. Each link consists of 16 lanes of 10, 12.5, or 15 Gbps.

IP Core supports 600 Gbps chip-to-chip interface.

Open-Silicon, Inc.    Milpitas, CA 95035
Apr 11, 2012 Supporting SerDes data rates up to 28 Gbps and 1-48 lanes, Interlaken IP Controller v6 conforms to Interlaken Retransmit Extension protocol definition and is suited for networking, storage, and high-performance computing products. Unit offers multiple user-data interface options, including 128-bit or 256-bit wide with 1, 2, or 4 segments. In addition, core enables multiple configurations, such as single 600 Gbps interface or four 150 Gbps interfaces, selected at power-up.

Controller IP Core enhances chip-to-chip serial interfaces.

Open-Silicon, Inc.    Milpitas, CA 95035
Mar 16, 2011 Providing flexibility needed to facilitate board-level design for high-speed chip-to-chip serial interfaces, Interlaken core features fully configurable SerDes lane mapping between logical and physical SerDes lanes. HiFlex architecture is included along with Interlaken-LA, In-Band and Out-of-Band flow control, multiple UI options, flexible statistics counters, and built-in interrupt structures. Core can scale from 10 to 300+ Gbps of bandwidth.