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Faraday Technology Corporation
No.5, Li-Hsin Rd.III, Hsinchu Science Park
Hsinchu City, Taiwan

Detailed Contact Information:
Cell Libraries and Memory Compilers minimize die area.   Return to story
Company Information:
Faraday Technology Corporation
No.5, Li-Hsin Rd.III, Hsinchu Science Park
Hsinchu City  300   Taiwan
Phone: 886.3.578.7888
FAX: 886.3.578.7889
http://www.faraday-tech.com
Marketing:
Carol Yang
Taiwan
Phone: 886.3.5787888 ext 4047
Send email  E-mail this person
 
 
Latest New Product News from Faraday Technology Corporation
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Cell Libraries and Memory Compilers minimize die area.

Faraday Technology Corporation    Hsinchu City, 300
Apr 29, 2014 Available in UMC 28 nm HPM and HLP processes, 28 nm Cell Libraries include 7-track miniLib™, 9-track generic libraries, and 12-track UHS-Lib™, which optimizes performance of ARM CPU cores for up to 1.5 GHz clock rate. Cell libraries provide low power management of PSK cells, as well as multi-Vt and multi-channel length options. To mitigate challenges of process variation associated with advance nodes such as 28 nm, memory compilers provide configurability with different types of assist circuits.

CPU Chip interfaces with variety of FPGA devices.

Faraday Technology Corporation    Hsinchu City, 300
Feb 28, 2007 Based on embedded 190 MHz ARM(TM) core, FPGACompanion CPU chip comes with complete set of peripherals, from USB 2.0 and Ethernet I/Os to DRAM and flash memory controllers. All I/Os are connected together via AMBA 2.0 system bus, and intelligent Direct Memory Access engine enables I/O devices to be accessible to FPGA connecting to it. Additional features include 8-channel ADC, AES-DES Cipher coprocessor, and built-in AHB bus header for external FPGA connectivity.

Application Specific IC suits communication applications.

Faraday Technology Corporation    Hsinchu City, 300
Oct 18, 2006 Incorporating MPCA(TM) Structured ASIC technology, SerDes-based Model NC Express(TM) offers pre-diffused communication controllers, 8 programmable multi-protocol SerDes channels, 400/533 MHz DDR-2 memory controller with ECC, and ARM(TM) v4 compatible CPU. With system-level IP integration, device is suitable for SoC designs targeting power-sensitive applications such as network protocol bridges, NAS, and home gateway designs.

Structured ASIC has almost one million logic gates.

Faraday Technology Corporation    Hsinchu City, 300
May 25, 2006 Along with 900,000 NAND-2 equivalent programmable logic gates, FIT-18 Template(TM) features 400 I/O pins, 98 of which can be configured for PCI/PCI-X interfaces. It is targeted at applications needing 5 V tolerant PCI/PCI-X I/Os in chip design. Implemented in 0.18 Ám process, product provides 80 KB SRAMs in single- and dual-port configurations for en-route data buffering. Other on-chip functions include PLL, DLL, OSC, and power-on-reset.




Other Company News From Faraday Technology Corporation

Jul 17, 2007

Faraday Technology Enhances PowerSmart(TM) Design Flow to Include Sequence's RTL Power Analysis Tool


Jan 28, 2007

Oki, Faraday Technology, and UMC/UMCJ Partner to Deliver 90 nm and below Design-to-Manufacture Services for Consumer Market


Jun 22, 2006

Faraday Showcases Networking and Multimedia ASIC and IP Solutions at ESEC Tokyo






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