Stretch Unveils Second Generation Software Configurable Processor Architecture |
(Archive News Story - Products mentioned in this Archive News Story may or may not be available from the manufacturer.)
Stretch, Inc.
1322 Orleans Drive
Sunnyvale, CA, 94089
USA
Press release date: March 5, 2007
Optimized for Video and Wireless Processing, S6 Offers Unprecedented Price/Performance
SUNNYVALE, Calif., March 5 / -- Stretch® Inc. today announced its S6 Software Configurable Processor (SCP) architecture. Optimized specifically for high-performance video and wireless signal processing, the S6 Architecture offers unmatched price/performance in these demanding applications. At the heart of the new architecture are three technology innovations: the second-generation Instruction Set Extension Fabric (ISEF), the Processor Array, and the Programmable Accelerator. The combination of these advancements provides unprecedented single-chip compute power and the ability to easily scale to multi-chip implementations for the most compute- intensive applications.
Commenting on the announcement, Craig Lytle, president and CEO, said, "We are very excited about the new S6 Architecture. The S6000 family of devices will revolutionize the way in which people think of high performance signal processing solutions. Building on our experience with our groundbreaking S5 family of devices, and working very closely with our customers, we created a new architecture that delivers a price/performance point second to none in the industry."
Unrivaled Compute Density for Video Applications
The S6 Architecture enables previously unattainable, single-chip implementations of applications such as H.264 High Definition encoding. A single S6000 family device can perform 4 channels of 4CIF/D1 H.264 BP encoding at 30fps or 16 channels of CIF resolution at 30fps, enabling H.264 encoding at less than $1.60/channel.
Second Generation S6 SCP Engine
The S6 SCP Engine has Stretch's second generation Instruction Set Extension Fabric (ISEF) embedded directly within the Tensilica® Xtensa® LX dual-issue VLIW Processor architecture.
The ISEF is a software configurable compute fabric that enables system designers to extend the processor instruction set and to define new instructions using C/C++ code. These "extension instructions" are then automatically synthesized, placed, and routed into the ISEF. Stretch has made several key improvements to the ISEF for the S6 architecture family, resulting in improved performance and reduced die area. In addition to enhancements to the compute elements in the ISEF, 64KB of distributed ISEF RAM (IRAM) has been added to allow for the storage of data within the ISEF itself. To support the enhanced processing capabilities of the architecture, a dedicated high speed DMA channel has been added to ensure that data is always available. Optimization of the ISEF compute elements and routing structures provide 300MHz operation, three times the performance of the original architecture. The new ISEF fabric can be dynamically reconfigured in less than thirty micro seconds, four times faster than the original fabric.
By using the Xtensa LX dual-issue VLIW architecture, the Stretch Compiler technology may now pack multiple instructions in a single issuance, enabling up to twice the performance of the previous processor architecture.
"We have dramatically increased the performance of the S6 SCP Engine through technology innovations, improved data transfer, and the usage of VLIW technology," stated Dr. Albert Wang, Stretch founder and CTO.
Processor Array Technology Enables Scalable System Design
The increasing complexity and diversity of video and wireless standards are driving companies to create scalable systems with varying degrees of processing power, depending upon the application requirements. To enable its customers to easily create systems of varying compute levels, Stretch developed the Processor Array solution. At the physical layer, each S6 device can interface with up to 4 other processors through dedicated 1.2GB/S DDR interface banks, allowing system architects to create processor topologies best suited for their application. So that the processor is not burdened with Processor Array functions, each S6 device has a dedicated processor network interface and switch circuitry to accommodate inter-processor communication. At the software layer, programmers can dedicate tasks, establish communication channels between processors, and even share resources between processors using a rich library of BIOS calls or custom-created C/C++ code.
"The Processor Array enables customers to use a single processor architecture and easily scale from multi-channel, SD resolution encoding or wireless CPE applications up to the most demanding High-Definition broadcast encoding/transcoding or wireless basestation applications," added Dr. Wang.
Programmable Accelerator Speeds High-Performance Design
Stretch accelerates common bottlenecks in video and wireless processing through a software Programmable Accelerator, dramatically improving the performance of 4 compute-intensive functions:
o Entropy Encoding: Supports CABAC for H.264 Main Profile Encoding and CAVLC for H.264 Baseline Profile. o Motion Estimation: Accelerates sum-of-absolute-differences (SAD) calculations up to 64Giga-SADs/S for Motion Estimation in algorithms such as H.264 and MPEG4. o Encryption: Accelerates commonly used encryption protocols, such as AES and 3DES. o Audio: Uses the Tensilica Xtensa HiFi-2 Audio Engine, providing its customers with over 19 different audio codecs.
All the Programmable Accelerator functions are accessed through a library of optimized object-code calls, enabling customers to quickly develop high- performance video and wireless processing designs.
"Through our customer engagements, we saw several opportunities to develop custom circuitry to accelerate common functions in video and wireless applications. Rather than create custom RTL blocks, we used a programmable approach that increases the flexibility and number of functions that can be accelerated using the same silicon real estate," said Craig Lytle.
Robust System Integration
The S6000 family of devices has a rich set of I/O connectivity for seamless integration with system elements for the most demanding signal processing applications including:
o Quad High-Speed Dataports: gluelessly interfaces with leading image sensors and wireless transceivers. o PCI-Express Interface: x1 and x4 channel connections in root complex or end-point configurations for PC add-in card applications or host processor communication and data transfer. o Triple-Speed Ethernet MAC: for seamless interface to high speed networks.
Complete Software Support
The S6000 devices are supported by the Stretch Integrated Development Environment, which includes a code editor, an optimizing compiler, and an instruction set simulator. Also available is a comprehensive library of optimized code supporting DSP functions, wireless signal processing functions, and complete H.264 and MJPEG encoders and decoders.
Availability and Pricing
The first member of the S6000 Family, the S6105, will be available in the third quarter of 2007. 50,000 unit pricing for the S6105 is $25 in 2008.
About Stretch
Stretch Inc. is delivering a family of software configurable processors, the first to embed programmable logic within the processor. Using familiar C/C++ programming tools, system developers automatically configure Stretch's off-the-shelf processors to achieve extraordinary performance, easy and rapid development, significant cost savings, and flexibility to address diverse markets and changing application needs. For more information, visit www.stretchinc.com.
Source: Stretch Inc.
CONTACT: Leslie-Ann Campbell of Stretch Inc., +1-408-543-2754, or Campbell@stretchinc.com; or Sacha Arts of Slider & Associates, +1-408-356- 3099, or sacha@sliderassociates.com, for Stretch Inc.
Web site: http://www.stretchinc.com/
|
|
|
|
|
|
| 
