STMicroelectronics Unveils Innovation Across the Board at ISSCC 2007
Geneva, February 12: STMicroelectronics (NYSE: STM), one of the world's most innovative semiconductor companies, will participate in nine events at this year's International Solid-State Circuits Conference (ISSCC) in San Francisco, California, during February 11-15, 2007. ST's contributions range from specific advances in fields as diverse as wireless interconnection, memories, RF building blocks, baseband signal processing and sensors, to an overview of the needs of the semiconductor industry at a time when microelectronics is becoming nanoelectronics.
In keeping with the theme of the conference - "The Four Dimensions of IC Design" - Joël Hartmann, Director of Crolles2 Alliance, STMicroelectronics, will present an invited paper on the opening day entitled "Towards a New Nanoelectronic Cosmology". This paper reviews the challenges inherent in further roadmap scaling and the emerging concept of Generalized Design-for-Manufacturability (GDfM), which requires tightly coupled physical, electrical, mechanical and process modeling and simulation - the four design dimensions in the new nanoelectronic cosmology.
In the RF building blocks session, ST and the University of Catania will describe a 0.25μm 2V CMOS Power Amplifier for GSM applications that delivers 3W output power with 55% power-added efficiency (PAE). A closed-loop mismatch protection method is implemented that enables the power amplifier to sustain a 20:1 load VSWR (Voltage Standing Wave Ratio) at full power. The circuit enables faster protection lock-in by reducing the number of low-frequency poles in the loop response. ST and the University of Pavia will also describe a novel 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning. Quadrature oscillators are widely used in narrowband wireless applications due to their high spectral purity at relatively low power levels. For wideband applications, duplicate oscillators are currently used but the oscillator described employs a frequency tuning method, based on the control of the magnetic field of a transformer, allowing continuous frequency variation over a very wide range.
In the Baseband Signal Processing session, a paper presented by ST, CEA-LETI, France Telecom R&D, and Mitsubitshi Electric ITE-TCL will describe the FAUST chip, which integrates a baseband processing architecture in which communications between Intellectual Property blocks are supported by an asynchronous network-on-chip (NoC). This distributed and modular structure facilitates physical implementation and power management. The 20-node NoC is implemented in 0.13μm CMOS technology and requires only 79.5mm to meet the needs of 100Mb/s telecom systems.
In the session entitled Proximity Data And Power Transmission, a joint research team from ST, the University of Bologna, Bologna, Italy and Fraunhofer IZM, Berlin will present mono and bi-directional asynchronous transmitter and receiver circuits that provide three-dimensional (3D) chip-to-chip data transmission through capacitive interconnections. 3D contactless data communication based on capacitive coupling is a very promising technology to overcome current SoC limitations caused by to interconnect problems. The communication scheme proposed provides a throughput per area of more than 22Mb/s/µm2 with an energy consumption of 80µW/Gb/s that is unrivalled by current solutions.
In the Sensors & MEMS session, a joint paper by ST, the University of Lecce, the University of Pavia, and the Italian research institute CNR-IMM will describe a complete CMOS integrated microsystem for detecting the direction of the Earth's magnetic field (whose full-scale value is on the order of 60μT). The system achieves 4° accuracy on the measured angle and provides a digital output. The system response is linear in the range of ±60μT, with a maximum non-linearity error of about 3% of full scale.
In the Analog & Power Management Techniques session, ST and the University of Brescia, Italy, will disclose a new charge-pump architecture for non-volatile memories. The main advantages compared to the state-of-the-art architectures in use today are the elimination of voltage threshold drops, compatibility with low-voltage devices and high frequency clock signals, higher power efficiency and removing the need to introduce high voltage transistors in the standard CMOS processes.
In the Trends in Wireless Systems session, a paper co-authored by researchers from ST and IEMN/ISEN, Lille, France, will describe a 2GHz 0.25µm SiGe BiCMOS oscillator with flip-chip mounted BAW (Bulk Acoustic Wave) resonator. The circuit achieves a phase noise of -124dBc/Hz at 100kHz carrier offset while consuming only 12mW in an IC footprint of 0.043mm2.
In the Non-Volatile Memories session, ST will present a 1.8V 1Gb 2b/cell NOR flash memory based on a time-domain voltage-ramp reading concept and designed in a 65nm technology. The program method, architecture and algorithm allow a 2.25MB/s programming throughput to be achieved, while the read mechanism allows 70ns random access time and a 400MB/s sustained read throughput via a DDR interface. The circuit innovation has resulted in the fastest read and write throughput for a NOR Flash ever reported, making it ideally suited for wireless applications.
About STMicroelectronics
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2006, the Company's net revenues were $9.85 billion and net earnings were $782 million. Further information on ST can be found at www.st.com.
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