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Mellanox Technologies Standardizes on Synopsys' Design Compiler Graphical Achieves Higher Operating Frequencies and Smaller Area

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Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA, 94043 4033
USA



Press release date: May 1, 2014

MOUNTAIN VIEW, Calif. –

Highlights:

• Design Compiler Graphical delivers 10 percent faster timing and tight correlation to IC Compiler

• Mellanox widely deploys Design Compiler Graphical to achieve challenging design goals within schedule

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Mellanox Technologies, a leading supplier of high-performance, end-to-end interconnect solutions for data center servers and storage systems, has standardized on Synopsys' Design Compiler® Graphical RTL Synthesis solution for the design of their interconnect products. High throughput with low latency is a key concern for data centers, requiring interconnect solution ICs to meet challenging performance requirements. To achieve these goals, Mellanox Technologies has widely deployed Design Compiler Graphical, a key component of Synopsys' Galaxy™ Design Platform and is realizing 10 percent higher performance, lower area and a highly convergent design flow.

"High-throughput chips are critical to success in providing end-to-end InfiniBand and Ethernet-based interconnect solutions to our customers," said Tzvika Shmueli, senior director, backend chip design at Mellanox Technologies. "With Design Compiler Graphical, we are experiencing 10 percent faster timing and very tight correlation to IC Compiler, which enables us to identify and fix design issues early in the flow. Design Compiler Graphical has also helped us reduce area and is now a standard component of our design flow."

Design Compiler Graphical addresses challenging design requirements at both established and emerging process nodes. It includes shared technology with the Synopsys IC Compiler™ solution that takes physical effects, such as routing congestion and RC variation into consideration and delivers superior timing, area, routability and power results. The physical guidance passed to IC Compiler, brings synthesis timing and area estimations to within five percent of layout, resulting in fewer iterations and faster design closure.

"Market leaders, such as Mellanox, who are targeting high-performance data center solutions rely on Design Compiler Graphical to achieve aggressive timing objectives within tight schedules," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "The product's innovative synthesis technologies and tight links with the Galaxy Design Platform enable our customers to accelerate delivery of industry-leading products to their target markets."

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.

Editorial Contacts:

Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
lgmartin@mcapr.com

SOURCE Synopsys, Inc.

Web Site: http://www.synopsys.com  
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