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Cadence Design Systems, Inc.

2655 Seely Avenue, San Jose, CA, 95134, US

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Latest New Product News from
Cadence Design Systems, Inc.

Test & Measuring Instruments, Materials & Material Processing

Power Analyzer accelerates accurate early assessments.

August 7, 2015

Built on multi-threaded architecture, Cadence® Joules™ RTL Power Solution lets SoC designers analyze power consumption during design exploration. Rapid prototype technology enables this register-transfer level (RTL) power analysis solution to analyze designs of up to 20 million instances with gate-level accuracy within 15% of final power as signed off in Cadence Voltus™ IC Power Integrity Solution. Also, additional integration fosters system-level power analysis and optimization. Read More

Test & Measuring Instruments

PCB EDA Software makes design cycles shorter and predictable.

May 26, 2015

Promoting efficiency and productivity for PCB designers, Allegro® 16.6 includes Allegro PCB Designer Manufacturing Option that helps streamline development of release-to-manufacturing package for products. Allegro Rules Developer and Checker, also included, offers single source for all design rules checks (DRCs) within PCB, lets users develop custom fabrication and assembly rules, and provides relational geometric verification language. Read More


SoC Implementation Software accelerates optimized design delivery.

March 18, 2015

Driven by massively parallel architecture, Innovus™ Implementation System helps SoC developers accelerate delivery of designs with optimized power, performance, and area (PPA). Physical implementation solution typically provides 10%–20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10 nm FinFET processes and established process nodes. Features include GigaPlace solver-based placement technology, slack-driven routing, and full-flow multi-objective technology. Read More


EDA Software offers system-level design/synthesis platform.

February 27, 2015

Offering consistent environment from TLM through gates to maximize design and verification quality, Cadence® Stratus™ can be utilized across entire SoC design and addresses such real world challenges as ECO, low power, IP reuse, and routing congestion. Platform integrates Forte and Cadence technology and leverages sixth-generation, high-level synthesis core engine that provides usability, scalability, and QoR across full application space. Read More

Computer Hardware & Peripherals

Flexible Processors let users create custom instruction sets.

January 14, 2015

Blending fixed-architecture solutions with Application Specific Instruction-set Processor tools, Tensilica® Xtensa® LX6 and Xtensa 11 processors include core Xtensa instruction set architecture. Flexible length instruction extensions for Xtensa LX6 allow very long instruction word (VLIW) instructions from 4–16 bytes. Other features include option for run-time power-down of portions of cache memories, data cache block prefetch, and reduced dynamic switching power of processor logic gates. Read More

Computer Hardware & Peripherals, Mechanical Components & Assemblies

DSP IP Core supports 32-bit audio/voice processing.

January 8, 2015

Enabling emerging multi-channel object-based audio standards, Tensilica® HiFi 4 Audio/Voice DSP IP Core is suited for digital TV, set-top box, Blu-ray Disc, and automotive infotainment. Processor supports four 32 x 32-bit multiplier-accumulators per cycle with 72-bit accumulators for computationally intensive functions such as Fast Fourier Transform and finite impulse response. Four very long instruction word (VLIW) slot architecture is capable of issuing two 64-bit loads per cycle. Read More


SoC Verifier improves productivity and end product quality.

December 19, 2014

Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, Cadence® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test development using constraint solving technology. Tests run on all pre-silicon verification platforms. Read More


EDA Software supports mixed-signal designs.

November 3, 2014

Integrating FastSPICE technology and Spectre® XPS, Cadence® Virtuoso® Liberate™ AMS offers dynamic simulation characterization solution for large mixed-signal macro blocks such as phase locked loops, data converters, high-speed transceivers, and I/Os. Hybrid partitioning approach identifies circuit activity at block level to carve out critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models. Read More


Automotive EDA Software reduces ISO 26262 compliance effort.

October 30, 2014

Cadence® Incisive® automotive functional verification platform incorporates fault injection and safety verification technologies that help engineers automate ISO 26262 compliance for traceability, safety verification, and tool confidence level. Functionality automates manual verification of fault injection and result analysis for IP, SoC, and system designs. This is accomplished via Incisive Functional Safety Simulator and Functional Safety Analysis capability in Incisive vManager™. Read More

Test & Measuring Instruments, Computer Hardware & Peripherals, Mechanical Components & Assemblies

Verification IP supports all popular 3D memory standards.

October 30, 2014

Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory contents, error configurability, transaction callbacks, assertion reports, and built-in address manager. Read More

Computer Hardware & Peripherals

Multi-Protocol IP fosters DDR4/LPDDR4 migration sans redesign.

October 24, 2014

Scalable up to 3,200 Mbps, Cadence® DDR controller and PHY IP enables designers to take advantage of higher performance DDR4 and LPDDR4 DRAMs, when they become available, without requiring systems on chip (SoC) redesign. Single multi-protocol IP solution lets designers address changing memory requirements in consumer, mobile, and enterprise applications. Read More


MIPI SoundWire Controller IP fosters mobile adoption.

October 17, 2014

Available to facilitate adoption of SoundWire spec, MIPI® SoundWireSM Controller IP can be used to interface digital microphones or speakers directly into next-generation mobile SoC designs. Audio interface, targeted for mobile applications, can reduce area requirements by up to 50%. SoundWire digital audio interface specification enables bi-directional digital communication with focus on low complexity and low gate count. Read More


EDA Software delivers foundry-certified SPICE-level accuracy.

August 7, 2014

Cadence® Voltus™-Fi Custom Power Integrity Solution, as transistor-level electromigration and IR-drop (EMIR) solution, delivers foundry-certified, SPICE-level accuracy in power signoff to create fastest path to design closure. Enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, product lets designers shrink critical power signoff closure and analysis phase through such capabilities as voltage-based iteration method and integration with Cadence Virtuoso®. Read More


PCB EDA/CAD Software enhances product design process.

July 29, 2014

OrCAD® Engineering Data Management (EDM), collaboration and management environment for OrCAD Capture; OrCAD Library Builder, rapid automated part builder; and OrCAD Documentation Editor intelligent, automated PCB documentation environment accelerate mainstream PCB design process while promoting productivity and efficiency. Combination of these products helps shorten documentation time through automation and enhanced team environment. Read More

Test & Measuring Instruments, Software, Materials & Material Processing

Rapid Prototyping Platform supports low-power verification.

July 22, 2014

System Development Suite includes Cadence® Protium™ rapid FPGA prototyping platform for software development as well as IEEE 1801 low power standard verification and debug support in Cadence Palladium® XP II verification computing platform. These features enable system and semiconductor companies in mobile, consumer, networking and storage segments to address such design challenges as early software bring-up and reduced power consumption. Read More


EDA Software offers tool for RC extraction.

July 21, 2014

With massively parallel architecture, Cadence® Quantus™ QRC Extraction Solution accelerates design signoff and sets standard for performance by accelerating runtime for single and multi-corner extraction. Tool is TSMC certified for 16 nm FinFET designs, supports both SoC and custom/analog designs, and includes Quantus FS foundry-certified integrated random-walk field solver. Automated incremental extraction capability minimizes design closure turnaround time. Read More


EDA Software cuts die-package interconnect planning time.

May 30, 2014

Used early in design cycle, Cadence® OrbitIO™ provides rapid planning of interfaces across multiple fabrics. As part of overall co-design solution, Cadence OrbitIO integrates with Cadence SiP Layout and Cadence Encounter® digital implementation platform, allowing design teams to clearly communicate design intent throughout flow. Software can enable fabless semiconductor or systems companies to evaluate package route feasibility, and communicate route plan to package design resources. Read More

Mechanical Components & Assemblies

DDR4 PHY IP targets microserver market.

May 28, 2014

Built on 16 nm FinFET process, Cadence® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps. Read More


EDA Software accelerates timing closure of PCB interfaces.

March 13, 2014

Available within Cadence® Allegro PCB Designer, Allegro® TimingVision™ uses embedded timing engine to analyze entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on canvas. When combined with Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues. Read More

Mechanical Components & Assemblies

Imaging/Video Dataplane Processor handles complex functions.

February 27, 2014

Tensilica® Imaging and Video Processor-Enhanced Performance (IVP-EP) core is available as configurable core and complete, pre-built subsystem. Integrating DMA transfer engine with up to 10 GBps throughput and local memory throughput of 1,024 bits per cycle, 4-way VLIW architecture delivers parallelism intermixed with code-compact instructions, with 32-way vector SIMD dataset. Imaging-specific operations accelerate 8-, 16-, and 32-bit pixel data types and video operation patterns. Read More

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Cadence Design Systems, Inc.