Company News

Cadence Design Systems, Inc.

2655 Seely Avenue, San Jose, CA, 95134, USA

  • 408-943-1234

Latest New Product News from
Cadence Design Systems, Inc.

computer hardware & peripherals, electronic components & devices

Vision DSP targets embedded neural network applications.

May 4, 2016

Based on Cadence Tensilica Xtensa® architecture, Cadence® Tensilica® Vision P6 combines flexible hardware choices with library of vision/imaging DSP functions and applications. Device quadruples multiply-accumulate (MAC) performance compared to previous generation, and utilizes 8- and 16-bit arithmetic to optimize key vision functions such as convolution, FIR filters, and matrix multiplication. On-the-fly data compression minimizes memory footprint and bandwidth requirements. Read More


IC Packaging Design/Analysis Solution offers all necessary tools.

March 21, 2016

Focused on advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs, IC packaging design and analysis solution includes Cadence® OrbitIO™ Interconnect Designer, Cadence System-in-Package (SiP) Layout, and Cadence Physical Verification System (PVS). Capabilities enable multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB. Read More

electronic components & devices

Design IP supports TSMC 16FFC and 28HPC+ process technologies.

March 18, 2016

To help reduce time to market for designers of advanced SoCs, high-speed SerDes communication interfaces and low-latency Denali® DDR memory IP solutions support TSMC's 16 nm FinFET Compact (16FFC) and 28 nm HPC Plus (28HPC+) process technologies. Design IP is available for such industry standards as DDR, PCIe, MIPI, Ethernet, USB, DisplayPort, and 802.11. Read More


Enterprise Emulation Platform offers datacenter-class performance.

November 18, 2015

Able to execute up to 2,304 parallel jobs and scale up to 9.2 billion gates, Cadence® Palladium® Z1 has rack-based blade architecture and can be utilized across global design teams to verify complex SoCs. Virtual target relocation capability optimizes utilization, while payload allocation into available resources at run time helps avoid re-compiles. Along with versatility via 12+ models, this datacenter-class enterprise emulation platform offers up to 140 million gate/hr compile times. Read More

communication systems & equipment, electrical equipment & systems

IP Subsystem integrates USB Type-C, USB power delivery, and more.

October 27, 2015

IP subsystem enables development of single-chip solutions for combining video, audio, USB, and up to 100 W of power on one external connector. Mitigating project risk and facilitating SoC integration, pre-verified components include single-chip port controller IP that incorporates USB Type-C™, USB Power Delivery, and DisplayPort™ Alternate Mode (Alt Mode). USB 3.0 xHCI Host and Device certified controller IP can be combined into Dual Role Device Controller. Read More

mechanical components & assemblies

DSP Core enables 4K mobile imaging.

October 9, 2015

Designed to off-load vision and imaging functions from main CPU, Cadence® Tensilica® Vision P5 saves energy in image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection, augmented reality, and object tracking applications. Device features 1,024 bit memory interface with SuperGather™ technology; up to 4 vector ALU operations per cycle, each with up to 64-way data parallelism; and up to 5 instructions issued per cycle from 128-bit wide instruction. Read More

materials & material processing, test & measuring instruments

Power Analyzer accelerates accurate early assessments.

August 7, 2015

Built on multi-threaded architecture, Cadence® Joules™ RTL Power Solution lets SoC designers analyze power consumption during design exploration. Rapid prototype technology enables this register-transfer level (RTL) power analysis solution to analyze designs of up to 20 million instances with gate-level accuracy within 15% of final power as signed off in Cadence Voltus™ IC Power Integrity Solution. Also, additional integration fosters system-level power analysis and optimization. Read More

test & measuring instruments

PCB EDA Software makes design cycles shorter and predictable.

May 26, 2015

Promoting efficiency and productivity for PCB designers, Allegro® 16.6 includes Allegro PCB Designer Manufacturing Option that helps streamline development of release-to-manufacturing package for products. Allegro Rules Developer and Checker, also included, offers single source for all design rules checks (DRCs) within PCB, lets users develop custom fabrication and assembly rules, and provides relational geometric verification language. Read More


SoC Implementation Software accelerates optimized design delivery.

March 18, 2015

Driven by massively parallel architecture, Innovus™ Implementation System helps SoC developers accelerate delivery of designs with optimized power, performance, and area (PPA). Physical implementation solution typically provides 10%–20% better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10 nm FinFET processes and established process nodes. Features include GigaPlace solver-based placement technology, slack-driven routing, and full-flow multi-objective technology. Read More


EDA Software offers system-level design/synthesis platform.

February 27, 2015

Offering consistent environment from TLM through gates to maximize design and verification quality, Cadence® Stratus™ can be utilized across entire SoC design and addresses such real world challenges as ECO, low power, IP reuse, and routing congestion. Platform integrates Forte and Cadence technology and leverages sixth-generation, high-level synthesis core engine that provides usability, scalability, and QoR across full application space. Read More

computer hardware & peripherals

Flexible Processors let users create custom instruction sets.

January 14, 2015

Blending fixed-architecture solutions with Application Specific Instruction-set Processor tools, Tensilica® Xtensa® LX6 and Xtensa 11 processors include core Xtensa instruction set architecture. Flexible length instruction extensions for Xtensa LX6 allow very long instruction word (VLIW) instructions from 4–16 bytes. Other features include option for run-time power-down of portions of cache memories, data cache block prefetch, and reduced dynamic switching power of processor logic gates. Read More

computer hardware & peripherals, mechanical components & assemblies

DSP IP Core supports 32-bit audio/voice processing.

January 8, 2015

Enabling emerging multi-channel object-based audio standards, Tensilica® HiFi 4 Audio/Voice DSP IP Core is suited for digital TV, set-top box, Blu-ray Disc, and automotive infotainment. Processor supports four 32 x 32-bit multiplier-accumulators per cycle with 72-bit accumulators for computationally intensive functions such as Fast Fourier Transform and finite impulse response. Four very long instruction word (VLIW) slot architecture is capable of issuing two 64-bit loads per cycle. Read More


SoC Verifier improves productivity and end product quality.

December 19, 2014

Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, Cadence® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test development using constraint solving technology. Tests run on all pre-silicon verification platforms. Read More


EDA Software supports mixed-signal designs.

November 3, 2014

Integrating FastSPICE technology and Spectre® XPS, Cadence® Virtuoso® Liberate™ AMS offers dynamic simulation characterization solution for large mixed-signal macro blocks such as phase locked loops, data converters, high-speed transceivers, and I/Os. Hybrid partitioning approach identifies circuit activity at block level to carve out critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models. Read More


Automotive EDA Software reduces ISO 26262 compliance effort.

October 30, 2014

Cadence® Incisive® automotive functional verification platform incorporates fault injection and safety verification technologies that help engineers automate ISO 26262 compliance for traceability, safety verification, and tool confidence level. Functionality automates manual verification of fault injection and result analysis for IP, SoC, and system designs. This is accomplished via Incisive Functional Safety Simulator and Functional Safety Analysis capability in Incisive vManager™. Read More

computer hardware & peripherals, mechanical components & assemblies, test & measuring instruments

Verification IP supports all popular 3D memory standards.

October 30, 2014

Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory contents, error configurability, transaction callbacks, assertion reports, and built-in address manager. Read More

computer hardware & peripherals

Multi-Protocol IP fosters DDR4/LPDDR4 migration sans redesign.

October 24, 2014

Scalable up to 3,200 Mbps, Cadence® DDR controller and PHY IP enables designers to take advantage of higher performance DDR4 and LPDDR4 DRAMs, when they become available, without requiring systems on chip (SoC) redesign. Single multi-protocol IP solution lets designers address changing memory requirements in consumer, mobile, and enterprise applications. Read More


MIPI SoundWire Controller IP fosters mobile adoption.

October 17, 2014

Available to facilitate adoption of SoundWire spec, MIPI® SoundWire<sup>SM</sup> Controller IP can be used to interface digital microphones or speakers directly into next-generation mobile SoC designs. Audio interface, targeted for mobile applications, can reduce area requirements by up to 50%. SoundWire digital audio interface specification enables bi-directional digital communication with focus on low complexity and low gate count. Read More


EDA Software delivers foundry-certified SPICE-level accuracy.

August 7, 2014

Cadence® Voltus&trade;-Fi Custom Power Integrity Solution, as transistor-level electromigration and IR-drop (EMIR) solution, delivers foundry-certified, SPICE-level accuracy in power signoff to create fastest path to design closure. Enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, product lets designers shrink critical power signoff closure and analysis phase through such capabilities as voltage-based iteration method and integration with Cadence Virtuoso®. Read More


PCB EDA/CAD Software enhances product design process.

July 29, 2014

OrCAD® Engineering Data Management (EDM), collaboration and management environment for OrCAD Capture; OrCAD Library Builder, rapid automated part builder; and OrCAD Documentation Editor intelligent, automated PCB documentation environment accelerate mainstream PCB design process while promoting productivity and efficiency. Combination of these products helps shorten documentation time through automation and enhanced team environment. Read More

Other Company News from
Cadence Design Systems, Inc.