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Latest New Product News from
Cadence Design Systems, Inc.
Cadence® Incisive® automotive functional verification platform incorporates fault injection and safety verification technologies that help engineers automate ISO 26262 compliance for traceability, safety verification, and tool confidence level. Functionality automates manual verification of fault injection and result analysis for IP, SoC, and system designs. This is accomplished via Incisive Functional Safety Simulator and Functional Safety Analysis capability in Incisive vManager™. Read More
Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory contents, error configurability, transaction callbacks, assertion reports, and built-in address manager. Read More
Scalable up to 3,200 Mbps, Cadence® DDR controller and PHY IP enables designers to take advantage of higher performance DDR4 and LPDDR4 DRAMs, when they become available, without requiring systems on chip (SoC) redesign. Single multi-protocol IP solution lets designers address changing memory requirements in consumer, mobile, and enterprise applications. Read More
Available to facilitate adoption of SoundWire spec, MIPI® SoundWireSM Controller IP can be used to interface digital microphones or speakers directly into next-generation mobile SoC designs. Audio interface, targeted for mobile applications, can reduce area requirements by up to 50%. SoundWire digital audio interface specification enables bi-directional digital communication with focus on low complexity and low gate count. Read More
Cadence® Voltus™-Fi Custom Power Integrity Solution, as transistor-level electromigration and IR-drop (EMIR) solution, delivers foundry-certified, SPICE-level accuracy in power signoff to create fastest path to design closure. Enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, product lets designers shrink critical power signoff closure and analysis phase through such capabilities as voltage-based iteration method and integration with Cadence Virtuoso®. Read More
OrCAD® Engineering Data Management (EDM), collaboration and management environment for OrCAD Capture; OrCAD Library Builder, rapid automated part builder; and OrCAD Documentation Editor intelligent, automated PCB documentation environment accelerate mainstream PCB design process while promoting productivity and efficiency. Combination of these products helps shorten documentation time through automation and enhanced team environment. Read More
System Development Suite includes Cadence® Protium™ rapid FPGA prototyping platform for software development as well as IEEE 1801 low power standard verification and debug support in Cadence Palladium® XP II verification computing platform. These features enable system and semiconductor companies in mobile, consumer, networking and storage segments to address such design challenges as early software bring-up and reduced power consumption. Read More
With massively parallel architecture, Cadence® Quantus™ QRC Extraction Solution accelerates design signoff and sets standard for performance by accelerating runtime for single and multi-corner extraction. Tool is TSMC certified for 16 nm FinFET designs, supports both SoC and custom/analog designs, and includes Quantus FS foundry-certified integrated random-walk field solver. Automated incremental extraction capability minimizes design closure turnaround time. Read More
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Cadence Design Systems, Inc.