Detailed contact information:
EDA Software cuts die-package interconnect planning time. Return to story
Latest New Product News from
Cadence Design Systems, Inc.
Blending fixed-architecture solutions with Application Specific Instruction-set Processor tools, Tensilica® Xtensa® LX6 and Xtensa 11 processors include core Xtensa instruction set architecture. Flexible length instruction extensions for Xtensa LX6 allow very long instruction word (VLIW) instructions from 4–16 bytes. Other features include option for run-time power-down of portions of cache memories, data cache block prefetch, and reduced dynamic switching power of processor logic gates. Read More
Enabling emerging multi-channel object-based audio standards, Tensilica® HiFi 4 Audio/Voice DSP IP Core is suited for digital TV, set-top box, Blu-ray Disc, and automotive infotainment. Processor supports four 32 x 32-bit multiplier-accumulators per cycle with 72-bit accumulators for computationally intensive functions such as Fast Fourier Transform and finite impulse response. Four very long instruction word (VLIW) slot architecture is capable of issuing two 64-bit loads per cycle. Read More
Intended for use-case, scenario-based software driven system-on-chip (SoC) verification, Cadence® Perspec™ System Verifier reduces complex test development to days while allowing design teams to reproduce, find, and fix complex bugs. Graphical specification of system-level verification scenarios and definition of SoC topology and actions automates system-level, coverage-driven test development using constraint solving technology. Tests run on all pre-silicon verification platforms. Read More
Integrating FastSPICE technology and Spectre® XPS, Cadence® Virtuoso® Liberate™ AMS offers dynamic simulation characterization solution for large mixed-signal macro blocks such as phase locked loops, data converters, high-speed transceivers, and I/Os. Hybrid partitioning approach identifies circuit activity at block level to carve out critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models. Read More
Cadence® Incisive® automotive functional verification platform incorporates fault injection and safety verification technologies that help engineers automate ISO 26262 compliance for traceability, safety verification, and tool confidence level. Functionality automates manual verification of fault injection and result analysis for IP, SoC, and system designs. This is accomplished via Incisive Functional Safety Simulator and Functional Safety Analysis capability in Incisive vManager™. Read More
Supporting Wide I/O 2, HMC, HBM, and DDR4-3DS Standards, Verification IP enables designers to accelerate verification of memory interfaces and achieve system-on-chip verification closure for compute server applications, mobile devices, high-performance graphics, and network applications. Advanced features include direct memory access for read, write, save, preload, and comparison of memory contents, error configurability, transaction callbacks, assertion reports, and built-in address manager. Read More
Scalable up to 3,200 Mbps, Cadence® DDR controller and PHY IP enables designers to take advantage of higher performance DDR4 and LPDDR4 DRAMs, when they become available, without requiring systems on chip (SoC) redesign. Single multi-protocol IP solution lets designers address changing memory requirements in consumer, mobile, and enterprise applications. Read More
Available to facilitate adoption of SoundWire spec, MIPI® SoundWireSM Controller IP can be used to interface digital microphones or speakers directly into next-generation mobile SoC designs. Audio interface, targeted for mobile applications, can reduce area requirements by up to 50%. SoundWire digital audio interface specification enables bi-directional digital communication with focus on low complexity and low gate count. Read More
Other Company News from
Cadence Design Systems, Inc.