Company News

Cadence Design Systems, Inc.

2655 Seely Ave., San Jose, CA, 95134, US

  • 408-943-1234
  • 800-746-6223
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Latest New Product News from
Cadence Design Systems, Inc.


MIPI SoundWire Controller IP fosters mobile adoption.

October 17, 2014

Available to facilitate adoption of SoundWire spec, MIPI® SoundWireSM Controller IP can be used to interface digital microphones or speakers directly into next-generation mobile SoC designs. Audio interface, targeted for mobile applications, can reduce area requirements by up to 50%. SoundWire digital audio interface specification enables bi-directional digital communication with focus on low complexity and low gate count. Read More


EDA Software delivers foundry-certified SPICE-level accuracy.

August 7, 2014

Cadence® Voltus™-Fi Custom Power Integrity Solution, as transistor-level electromigration and IR-drop (EMIR) solution, delivers foundry-certified, SPICE-level accuracy in power signoff to create fastest path to design closure. Enabled by Cadence Spectre® Accelerated Parallel Simulator signoff SPICE simulation, product lets designers shrink critical power signoff closure and analysis phase through such capabilities as voltage-based iteration method and integration with Cadence Virtuoso®. Read More


PCB EDA/CAD Software enhances product design process.

July 29, 2014

OrCAD® Engineering Data Management (EDM), collaboration and management environment for OrCAD Capture; OrCAD Library Builder, rapid automated part builder; and OrCAD Documentation Editor intelligent, automated PCB documentation environment accelerate mainstream PCB design process while promoting productivity and efficiency. Combination of these products helps shorten documentation time through automation and enhanced team environment. Read More

Software, Test & Measuring Instruments, Materials & Material Processing

Rapid Prototyping Platform supports low-power verification.

July 22, 2014

System Development Suite includes Cadence® Protium™ rapid FPGA prototyping platform for software development as well as IEEE 1801 low power standard verification and debug support in Cadence Palladium® XP II verification computing platform. These features enable system and semiconductor companies in mobile, consumer, networking and storage segments to address such design challenges as early software bring-up and reduced power consumption. Read More


EDA Software offers tool for RC extraction.

July 21, 2014

With massively parallel architecture, Cadence® Quantus™ QRC Extraction Solution accelerates design signoff and sets standard for performance by accelerating runtime for single and multi-corner extraction. Tool is TSMC certified for 16 nm FinFET designs, supports both SoC and custom/analog designs, and includes Quantus FS foundry-certified integrated random-walk field solver. Automated incremental extraction capability minimizes design closure turnaround time. Read More


EDA Software cuts die-package interconnect planning time.

May 30, 2014

Used early in design cycle, Cadence® OrbitIO™ provides rapid planning of interfaces across multiple fabrics. As part of overall co-design solution, Cadence OrbitIO integrates with Cadence SiP Layout and Cadence Encounter® digital implementation platform, allowing design teams to clearly communicate design intent throughout flow. Software can enable fabless semiconductor or systems companies to evaluate package route feasibility, and communicate route plan to package design resources. Read More

Mechanical Components & Assemblies

DDR4 PHY IP targets microserver market.

May 28, 2014

Built on 16 nm FinFET process, Cadence® DDR4 PHY IP supports unbuffered dual in-line memory module with features such as cyclic redundancy check and data bus inversion. Product implements 4x clocking to minimize duty cycle distortion, multi-band power isolation for noise immunity, and I/O with slew rate control. Combination of 16 nm technology and Cadence's architecture helps customers realize maximum performance of DDR4 standard, which is specified to scale up to 3,200 Mbps. Read More


EDA Software accelerates timing closure of PCB interfaces.

March 13, 2014

Available within Cadence® Allegro PCB Designer, Allegro® TimingVision™ uses embedded timing engine to analyze entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on canvas. When combined with Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues. Read More

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Cadence Design Systems, Inc.